公开(公告)号：US20240395896A1

公开(公告)日：2024-11-28

申请号：US18786751

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Chih-Hsuan Chen ,  Yu-Kuan Lin

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H10B10/00

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yittrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.

公开(公告)号：US11864368B2

公开(公告)日：2024-01-02

申请号：US17830967

申请日：2022-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jordan Hsu ,  Yu-Kuan Lin ,  Shau-Wei Lu ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Hung Lo

IPC: H10B10/00 ,  H01L27/092 ,  H10B99/00 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/088 ,  H01L29/49

CPC classification number: H10B10/12 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/66803 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H10B99/00

Abstract: A static random access memory (SRAM) cell includes substrate, a first semiconductor fin, a first gate structure, a second semiconductor fin, and a second gate structure. The substrate has a first p-well and an n-well bordering the first p-well. The first semiconductor fin extends within the first p-well. The first gate structure extends across the first semiconductor fin and forms a first write-port pull-down transistor with the first semiconductor fin. The second semiconductor fin extends within the n-well. The second gate structure extends across the second semiconductor fin and forms a first write-port pull-up transistor with the second semiconductor fin. A channel region of the first write-port pull-down transistor has a higher doping concentration than a channel region of the first write-port pull-up transistor.

公开(公告)号：US11641729B2

公开(公告)日：2023-05-02

申请号：US16721657

申请日：2019-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jordan Hsu ,  Yu-Kuan Lin ,  Shau-Wei Lu ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Hung Lo

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L29/49 ,  H01L27/105

Abstract: A method for manufacturing a SRAM cell includes forming a first p-well in a semiconductor substrate; forming a first semiconductor fin extending within the first p-well; forming a first mask layer over the first semiconductor fin; patterning the first mask layer to expose a first channel region of the first semiconductor fin, while leaving a second channel region of the first semiconductor fin covered by the first mask layer; with the patterned first mask layer in place, doping the first channel region of the first semiconductor fin with a first dopant; after doping the first channel region of the first semiconductor fin, removing the first mask layer from the second channel region; and forming a first gate structure extending across the first channel region of the first semiconductor fin and a second gate structure extending across the second channel region of the first semiconductor fin.

公开(公告)号：US11621267B2

公开(公告)日：2023-04-04

申请号：US16854770

申请日：2020-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC: H01L27/11 ,  G11C11/412 ,  H01L29/66 ,  H01L23/522 ,  H01L27/02 ,  H01L21/768

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

公开(公告)号：US20230059973A1

公开(公告)日：2023-02-23

申请号：US17982163

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L21/8238 ,  H01L27/092 ,  G11C11/412 ,  H01L27/11 ,  H01L21/762 ,  G06F30/392

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

公开(公告)号：US11587927B2

公开(公告)日：2023-02-21

申请号：US16827315

申请日：2020-03-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Yu-Kuan Lin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L21/308 ,  H01L29/66 ,  H01L21/3065

Abstract: A device includes a semiconductor substrate having a first region and a second region. The device further includes a first pair of fin structures within the first region. The device further includes a second pair of fin structures within the second region. A top surface of the semiconductor surface between fin structures within the first pair is higher than a top surface of the semiconductor surface between the first pair and the second pair.

公开(公告)号：US11563013B2

公开(公告)日：2023-01-24

申请号：US17035371

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen Su ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H01L21/8234 ,  H01L21/768 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

公开(公告)号：US20220383943A1

公开(公告)日：2022-12-01

申请号：US17877049

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chia-Hao Pao ,  Choh Fei Yeap ,  Yu-Kuan Lin ,  Kian-Long Lim

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/419

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

公开(公告)号：US11355499B2

公开(公告)日：2022-06-07

申请号：US16721632

申请日：2019-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jordan Hsu ,  Yu-Kuan Lin ,  Shau-Wei Lu ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Hung Lo

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/49 ,  H01L27/105

Abstract: A static random access memory (SRAM) cell includes substrate, a first semiconductor fin, a first gate structure, a second semiconductor fin, and a second gate structure. The substrate has a first p-well and an n-well bordering the first p-well. The first semiconductor fin extends within the first p-well. The first gate structure extends across the first semiconductor fin and forms a first write-port pull-down transistor with the first semiconductor fin. The second semiconductor fin extends within the n-well. The second gate structure extends across the second semiconductor fin and forms a first write-port pull-up transistor with the second semiconductor fin. A channel region of the first write-port pull-down transistor has a higher doping concentration than a channel region of the first write-port pull-up transistor.

公开(公告)号：US11239121B2

公开(公告)日：2022-02-01

申请号：US17012530

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Chen ,  Jui-Lin Chen ,  Yu-Kuan Lin

IPC: H01L21/8238 ,  H01L27/11 ,  H01L23/522 ,  H01L21/768

Abstract: A method of forming a semiconductor device includes providing a structure that includes a substrate, a first fin and a second fin, a first gate structure engaging the first fin, and a second gate structure engaging the second fin; depositing a dielectric layer over the first and second gate structures; etching the dielectric layer, thereby forming a first gate contact opening exposing the first gate structure and a second gate contact opening exposing the second gate structure, wherein the first gate contact opening has a first length that is larger than a second length of the second gate contact opening; and filling the first and second gate contact openings with conductive material, thereby forming a first gate contact engaging the first gate structure and a second gate contact engaging the second gate structure.