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    Capacitor structure with low capacitance
    24.
    发明授权
    Capacitor structure with low capacitance 有权

    公开(公告)号：US10998397B2

    公开(公告)日：2021-05-04

    申请号：US16834265

    申请日：2020-03-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tai-Yi Chen ,  Chung-Chieh Yang ,  Yung-Chow Peng

    IPC: H01L49/02 ,  H01L23/522

    Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

    Low power comparator and self-regulated device
    25.
    发明授权
    Low power comparator and self-regulated device 有权

    公开(公告)号：US10823765B2

    公开(公告)日：2020-11-03

    申请号：US15965994

    申请日：2018-04-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yung-Chow Peng ,  Chung-Peng Hsieh

    IPC: G01R19/00 ,  G05F1/66 ,  G05F1/44

    Abstract: A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.

    Circuits and methods for reducing kickback noise in a comparator
    26.
    发明授权
    Circuits and methods for reducing kickback noise in a comparator 有权

    公开(公告)号：US10819316B2

    公开(公告)日：2020-10-27

    申请号：US16457459

    申请日：2019-06-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Ho Chang ,  Jaw-Juinn Horng ,  Yung-Chow Peng

    IPC: H03K3/013 ,  H03K3/023

    Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

    LOW POWER COMPARATOR AND SELF-REGULATED DEVICE
    27.
    发明申请
    LOW POWER COMPARATOR AND SELF-REGULATED DEVICE 审中-公开

    公开(公告)号：US20190277891A1

    公开(公告)日：2019-09-12

    申请号：US15965994

    申请日：2018-04-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yung-Chow Peng ,  Chung-Peng Hsieh

    IPC: G01R19/00 ,  G05F1/44 ,  G05F1/66

    Abstract: A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.

    In situ on the fly on-chip variation measurement
    29.
    发明授权
    In situ on the fly on-chip variation measurement 有权
    原位实时片上变化测量

    公开(公告)号：US09448281B2

    公开(公告)日：2016-09-20

    申请号：US14134259

    申请日：2013-12-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jinn-Yeh Chien ,  Yung-Chow Peng ,  Chung-Chieh Yang ,  Kuan-Yu Lin

    IPC: G01R31/28 ,  G01R31/317

    CPC classification number: G01R31/31727 ,  G01R31/31718 ,  G01R31/31725

    Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.

    Abstract translation: 提供集成电路设计的方法和电路。 提供了用于集成电路的第一电子设计文件。 该集成电路的第一电子设计文件具有定时测量电路。 基于第一个电子设计文件，制造了许多集成电路。 这些制造的集成电路具有布置在其上的预定位置的各自的定时测量电路。 定时测量电路用于在集成电路上测量受制造变化的各个定时延迟值的数量。 测量的定时延迟值用于设置自动放置和布线工具如何在第二个电子设计文件中排列块，该第二个电子设计文件在测量定时延迟值之后被路由，以考虑任何测量的制造变化。

    Integrated Circuit With Transistor Array And Layout Method Thereof
    30.
    发明申请
    Integrated Circuit With Transistor Array And Layout Method Thereof 有权
    具有晶体管阵列的集成电路及其布局方法

    公开(公告)号：US20150241902A1

    公开(公告)日：2015-08-27

    申请号：US14192121

    申请日：2014-02-27

    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

    Inventor： Ching-Ho Chang ,  Jaw-Juinn Horng ,  Yung-Chow Peng

    IPC: G05F3/26 ,  G06F17/50 ,  H01L27/088

    CPC classification number: G05F3/262 ,  G06F17/5072 ,  H01L27/0617 ,  H01L27/0705 ,  H01L27/10 ,  H01L29/42376

    Abstract: An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together. The transistors are implemented within a transistor array. The transistors are electrically connected between a first reference terminal and a second reference terminal. A non-dominator part of the transistors adjacent to the first reference terminal are implemented at corner regions of the transistor array.

    Abstract translation: 集成电路包括多个晶体管。 晶体管串联电连接并且其各自的栅极连接在一起。 晶体管被实现在晶体管阵列内。 晶体管电连接在第一参考端和第二参考端之间。 与第一参考端相邻的晶体管的非支配部分实现在晶体管阵列的角区。

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