公开(公告)号：US6147919A

公开(公告)日：2000-11-14

申请号：US274245

申请日：1999-03-23

申请人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

发明人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

IPC分类号： H01L27/10 ,  G11C7/06 ,  G11C7/12 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C7/12

摘要： A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks. The local drivers apply a selection signal to the second selection lines according to a selection signal from the first selection lines. The write-only column selection lines are controlled by signals that are used to control the sense amplifiers.

摘要翻译： 半导体存储器具有排列成阵列的存储单元，布置在每个存储单元列中的直接型读出放大器，用于向要被访问的存储单元写入数据和从存储单元读取数据;列选择线，用于选择读取放大器 涉及要访问的存储器单元的列，只读列选择线，用于选择存储单元被访问以涉及要访问的存储器单元的行的读出放大器以写入数据，以及本地驱动器。 读出放大器在每行中分组成读出放大器模块。 只写列选择线由用于选择读入放大器块的第一选择线组成，所述读出放大器块包括要被存取的存储单元以进行数据写入，第二选择线用于选择包含在所选择的读出放大器块中的读出放大器 。 本地驱动器根据来自第一选择线的选择信号向第二选择线施加选择信号。 只写列选择线由用于控制读出放大器的信号控制。

公开(公告)号：US20090145395A1

公开(公告)日：2009-06-11

申请号：US12289509

申请日：2008-10-29

申请人： Yuki Ishii ,  Kazuhiro Yoshizumi ,  Naoki Suganuma ,  Shinichiro Takahashi ,  Ryo Suzuki

发明人： Yuki Ishii ,  Kazuhiro Yoshizumi ,  Naoki Suganuma ,  Shinichiro Takahashi ,  Ryo Suzuki

IPC分类号： F01M11/06 ,  F01M11/00

CPC分类号： F01M11/0004 ,  F01M2011/0008 ,  F01M2011/002

摘要： An oil pan structure includes a plurality of reinforcement beads of several kinds. An engine utilizes the oil pan, whereby the strength and vibration-rigidity (rigidity against vibration) of the oil pan and the engine are sufficiently enhanced so that a natural frequency of the oil pan and the engine therewith becomes adjustable through a selection as to the numbers, locations, and sizes of the beads.

摘要翻译： 油盘结构包括多种多种加强珠。 发动机利用油盘，由此可以充分提高油底壳和发动机的强度和振动刚度（抗振动刚度），使得油底壳和发动机的固有频率可通过选择来调节 珠子的数量，位置和大小。

公开(公告)号：US07499809B2

公开(公告)日：2009-03-03

申请号：US11214581

申请日：2005-08-30

申请人： Makoto Nagura ,  Yuki Ishii ,  Hideyuki Ikeda ,  Takuji Kurozumi ,  Yoshiaki Togawa

发明人： Makoto Nagura ,  Yuki Ishii ,  Hideyuki Ikeda ,  Takuji Kurozumi ,  Yoshiaki Togawa

IPC分类号： G01N31/00

CPC分类号： G01N15/0211

摘要： In a measurement system, by suppressing the environmental changes of counter-flow of air, and temperature changes and the like, measurement can be accomplished with stable high precision and replication, and by providing a transparent cell 2 which stores a particles dispersed in a dispersion medium, and a light source which irradiates light onto the particles within the transparent cell 2, and multiple light detectors 5 scattered and arranged to detect the intensity of diffracted/scattered light produced by the irradiation of light, and a computer device 6 which calculates the particle size distribution of the particles based on the light intensity signal output from the light detectors 5, in addition to the establishment of cell storage space S which stores the transparent cell 2 and the equipment storage spaces S1 and S2 which store the light source 41a, the light detector 5, and the optical device 6, the equipment storage spaces S1 and S2 are given tight closed construction separate from the cell storage space S.

摘要翻译： 在测量系统中，通过抑制空气的逆流的环境变化和温度变化等，可以以稳定的高精度和复制度进行测量，并且通过提供将分散在分散体中的颗粒存储的透明电池2 介质以及将光照射到透明单元2内的微粒上的光源，以及散布并布置成检测由照射光产生的衍射/散射光的强度的多个光检测器5以及计算机 除了建立存储透明单元2的单元存储空间S和存储光源41a的设备存储空间S1和S2之外，基于从光检测器5输出的光强度信号，颗粒的粒度分布， 光检测器5和光学装置6，设备存储空间S1和S2分开给予紧密封闭结构 从细胞储存空间S.

公开(公告)号：US20060052944A1

公开(公告)日：2006-03-09

申请号：US11214581

申请日：2005-08-30

申请人： Makoto Nagura ,  Yuki Ishii ,  Hideyuki Ikeda ,  Takuji Kurozumi ,  Yoshiaki Togawa

发明人： Makoto Nagura ,  Yuki Ishii ,  Hideyuki Ikeda ,  Takuji Kurozumi ,  Yoshiaki Togawa

IPC分类号： G06F19/00

CPC分类号： G01N15/0211

摘要： In a measurement system, by suppressing the environmental changes of counter-flow of air, and temperature changes and the like, measurement can be accomplished with stable high precision and replication, and by providing a transparent cell 2 which stores a particles dispersed in a dispersion medium, and a light source which irradiates light onto the particles within the transparent cell 2, and multiple light detectors 5 scattered and arranged to detect the intensity of diffracted/scattered light produced by the irradiation of light, and a computer device 6 which calculates the particle size distribution of the particles based on the light intensity signal output from the light detectors 5, in addition to the establishment of cell storage space S which stores the transparent cell 2 and the equipment storage spaces S1 and S2 which store the light source 41a, the light detector 5, and the optical device 6, the equipment storage spaces S1 and S2 are given tight closed construction separate from the cell storage space S.

摘要翻译： 在测量系统中，通过抑制空气的逆流的环境变化和温度变化等，可以以稳定的高精度和复制度进行测量，并且通过提供将分散在分散体中的颗粒存储的透明电池2 介质以及将光照射到透明单元2内的微粒上的光源，以及散布并布置成检测由照射光产生的衍射/散射光的强度的多个光检测器5以及计算机 除了建立存储透明单元2的单元存储空间S和存储光源的设备存储空间S 1和S 2之外，基于从光检测器5输出的光强度信号，颗粒的粒度分布 如图41a，光检测器5和光学装置6，设备存储空间S1和S2被给予紧密结构 与细胞存储空间S分开。

公开(公告)号：US06628564B1

公开(公告)日：2003-09-30

申请号：US09339855

申请日：1999-06-25

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C808

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit resetting the word line by driving the word line connected to a memory cell and switching a reset level of the word line drive circuit at the time of the reset operation of the word line. Further, a semiconductor device includes a memory cell array formed by arranging a plurality of memory cells and a reset level switch circuit for selecting a first potential or a second potential and supplying the first potential or the second potential to the word line drive circuit.

摘要翻译： 半导体器件包括字线驱动电路，通过驱动连接到存储单元的字线并在字线的复位操作时切换字线驱动电路的复位电平来重置字线。 此外，半导体器件包括通过布置多个存储单元形成的存储单元阵列和用于选择第一电位或第二电位的复位电平开关电路，并将第一电位或第二电位提供给字线驱动电路。

公开(公告)号：US06614266B2

公开(公告)日：2003-09-02

申请号：US10006649

申请日：2001-12-10

申请人： Yuki Ishii ,  Kaoru Mori

发明人： Yuki Ishii ,  Kaoru Mori

IPC分类号： H03K19096

CPC分类号： G11C7/106 ,  G11C7/065 ,  G11C7/1051 ,  G11C11/4091 ,  G11C2207/2227 ,  H03K19/0016

摘要： A semiconductor integrated circuit having an active mode and a standby mode includes a node at which an internal circuit is connected to a latch circuit, the latch circuit storing a data signal output from the internal circuit. A level determination unit determines a logic level of the node in response to a control signal indicating the standby mode.

摘要翻译： 具有活动模式和待机模式的半导体集成电路包括内部电路连接到锁存电路的节点，所述锁存电路存储从内部电路输出的数据信号。 电平确定单元响应于指示待机模式的控制信号来确定节点的逻辑电平。

公开(公告)号：US06605963B2

公开(公告)日：2003-08-12

申请号：US09412590

申请日：1999-10-05

申请人： Ayako Kitamoto ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Hideki Kanou ,  Kuninori Kawabata ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

发明人： Ayako Kitamoto ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Hideki Kanou ,  Kuninori Kawabata ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

IPC分类号： H03K19185

CPC分类号： H03K19/0013 ,  H03K3/356113 ,  H03K17/102 ,  H03K19/00361 ,  H03K2217/0036

摘要： A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

摘要翻译： 公开了一种半导体集成电路，其包括具有预定功能的电路单元，例如通过多个晶体管的组合的电平移位器电路或驱动晶体管电路。 在电路单元的多个晶体管中，改变了在电路单元的待机期间适于关断的至少一个晶体管的源极电位。 优选地，半导体集成电路被配置为减少在电路单元的待机时段期间流过至少一个晶体管的源极和漏极之间的亚阈值电流，其在基于 以使得在晶体管的栅极和源极之间施加预定的偏置电压的方式使电路单元的待机时段。 还公开了一种在具有上述结构的半导体集成电路中切换至少一个晶体管的源极电位的方法。

公开(公告)号：US06172537B2

公开(公告)日：2001-01-09

申请号：US09286439

申请日：1999-04-06

申请人： Hideki Kanou ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Ayako Kitamoto ,  Toshikazu Nakamura ,  Kuninori Kawabata ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

发明人： Hideki Kanou ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Ayako Kitamoto ,  Toshikazu Nakamura ,  Kuninori Kawabata ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

IPC分类号： H03K1700

CPC分类号： G11C7/106 ,  G06F1/10 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/22 ,  G11C7/222 ,  H03K5/131 ,  H03K5/133 ,  H03L7/0814

摘要： A semiconductor device has a DLL circuit or the like for adjusting the phase of an external clock and producing an internal clock that lags behind by a given phase. The semiconductor device further includes a clock frequency judging unit for judging the frequency of a first clock on the basis of an indication signal indicating a delay value of the first clock in the DLL circuit or the like to output a control signal; and a clock selecting unit for selecting either one of the first clock and the second clock, in response to the control signal.

摘要翻译： 半导体器件具有用于调整外部时钟的相位的DLL电路等，并且产生在给定相位之后滞后的内部时钟。 半导体器件还包括时钟频率判定单元，用于根据指示DLL电路等中的第一时钟的延迟值的指示信号等来判定第一时钟的频率，以输出控制信号; 以及时钟选择单元，用于响应于控制信号选择第一时钟和第二时钟中的任一个。

公开(公告)号：US6072749A

公开(公告)日：2000-06-06

申请号：US166070

申请日：1998-10-05

申请人： Toshikazu Nakamura ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

发明人： Toshikazu Nakamura ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

IPC分类号： G11C16/02 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C16/06 ,  G11C8/00

CPC分类号： G11C7/1018

摘要： This invention is a memory device with a structure that has eliminated the logic circuit using I/O mask signal DQM from within the critical path from the clock CLK to the predecoder and column decoder for generating column selection signal CL. The logic circuit using I/O mask signal DQM within the critical path for generating column selection signals is eliminated, and the time from when the clock is supplied until the column selection signal is generated is made as short as possible. On the other hand, to make an I/O mask possible during burst write mode, drive control of the write amplifier is performed based on I/O mask signal DQM. Specifically, activation of the write amplifier is prohibited or allowed in response to the I/O mask signal DQM.

摘要翻译： 本发明是具有这样的结构的存储器件，该结构使用从时钟CLK到用于产生列选择信号CL的预解码器和列解码器的关键路径内的I / O掩码信号DQM消除了逻辑电路。 消除了用于产生列选择信号的关键路径内使用I / O掩码信号DQM的逻辑电路，并且从提供时钟直到产生列选择信号的时间尽可能地缩短。 另一方面，为了在突发写入模式期间使I / O掩模成为可能，基于I / O掩码信号DQM执行写入放大器的驱动控制。 具体地，响应于I / O掩码信号DQM，禁止或允许写入放大器的激活。

公开(公告)号：US08061325B2

公开(公告)日：2011-11-22

申请号：US12289509

申请日：2008-10-29

申请人： Yuki Ishii ,  Kazuhiro Yoshizumi ,  Naoki Suganuma ,  Shinichiro Takahashi ,  Ryo Suzuki

发明人： Yuki Ishii ,  Kazuhiro Yoshizumi ,  Naoki Suganuma ,  Shinichiro Takahashi ,  Ryo Suzuki

IPC分类号： F02B77/00

CPC分类号： F01M11/0004 ,  F01M2011/0008 ,  F01M2011/002

摘要： An oil pan structure includes a plurality of reinforcement beads of several kinds. An engine utilizes the oil pan, whereby the strength and vibration-rigidity (rigidity against vibration) of the oil pan and the engine are sufficiently enhanced so that a natural frequency of the oil pan and the engine therewith becomes adjustable through a selection as to the numbers, locations, and sizes of the beads.

摘要翻译： 油盘结构包括多种多种加强珠。 发动机利用油盘，由此可以充分提高油底壳和发动机的强度和振动刚度（抗振动刚度），使得油底壳和发动机的固有频率可通过选择来调节 珠子的数量，位置和大小。