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公开(公告)号：US07023048B2
公开(公告)日：2006-04-04
申请号：US10417269
申请日：2003-04-17
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115
摘要： The present invention enables to avoid a reduction in coupling ratio in a nonvolatile semiconductor memory device. The reduction is coupling ratio is caused due to difficulties in batch forming of a control gate material, an interpoly dielectric film material, and a floating gate material, the difficulties accompanying a reduction in word line width. Further, the invention enables to avoid damage caused in the batch forming on a gate oxide film. Before forming floating gates of memory cells of a nonvolatile memory, a space enclosed by insulating layers is formed for each of the floating gates of the memory cells, so that the floating gate is buried in the space. This structure is realized by processing the floating gates in a self alignment manner after depositing the floating gate material. Therefore, it is unnecessary to perform the batch forming of the control gate material, the interpoly dielectric film material, and the floating gate material in the case of processing the control gates, thereby ensuring adequate interpoly dielectric film capacitance.
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公开(公告)号：US06670671B2
公开(公告)日：2003-12-30
申请号：US10166145
申请日：2002-06-11
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a channel region between the source/drain diffusion layers, impurities of the same conductivity type as the well are doped in an area apart from the diffusion regions. By using as a mask the gate formed in advance, tilted ion implantation in opposite directions is performed to form the diffusion layers and heavily impurity doped region of the same conductivity type as the well in a self-alignment manner relative to the gate.
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公开(公告)号：US09153774B2
公开(公告)日：2015-10-06
申请号：US13884263
申请日：2010-12-06
申请人： Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Akio Shima , Kenzo Kurotsuchi , Takashi Kobayashi
发明人： Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Akio Shima , Kenzo Kurotsuchi , Takashi Kobayashi
IPC分类号： H01L27/06 , H01L45/00 , H01L27/102 , H01L29/792 , H01L27/24 , H01L27/115 , G11C13/00
CPC分类号： H01L45/1608 , G11C13/0004 , G11C2213/75 , H01L27/0688 , H01L27/1021 , H01L27/11578 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/7926 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.
摘要翻译： 当在叠层薄膜上除去形成在绝缘膜和栅电极交替层叠在一起的叠层膜的侧壁上的薄沟道半导体层时，包括沟道半导体层的垂直晶体管与栅电极之间的接触电阻， 并且防止形成在层叠膜上的位线上升。 作为其手段，电连接到沟道半导体层的导电层设置在堆叠膜的正上方。
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公开(公告)号：US08830740B2
公开(公告)日：2014-09-09
申请号：US13814104
申请日：2011-08-26
申请人： Yoshitaka Sasago , Hiroyuki Minemura , Takashi Kobayashi , Toshimichi Shintani , Satoru Hanzawa , Masaharu Kinoshita
发明人： Yoshitaka Sasago , Hiroyuki Minemura , Takashi Kobayashi , Toshimichi Shintani , Satoru Hanzawa , Masaharu Kinoshita
CPC分类号： G11C13/0004 , G11C2213/71 , G11C2213/72 , G11C2213/75 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.
摘要翻译： 本发明的目的是提高相变存储器的重写传输速率和可靠性。 为了实现该目的，在串行（2）和位线（3）之间串联提供多个相变存储单元（SMC或USMC），并且具有并联连接的选择元件和存储元件 彼此完全设置，之后，与数据模式对应的单元的一部分被重置。 或者，执行相反的操作。
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公开(公告)号：US08563961B2
公开(公告)日：2013-10-22
申请号：US13515435
申请日：2010-12-13
申请人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikastsu Takaura
发明人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikastsu Takaura
IPC分类号： H01L47/00
CPC分类号： H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N> = 1）个第一栅极间绝缘层（11-15）和N个第一半导体 层（21p-24p）在基板的高度方向交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。
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公开(公告)号：US20130234101A1
公开(公告)日：2013-09-12
申请号：US13884331
申请日：2010-11-22
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L27/1157 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/66833 , H01L29/7926 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1616 , H01L45/1683
摘要： A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
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公开(公告)号：US20120248399A1
公开(公告)日：2012-10-04
申请号：US13515435
申请日：2010-12-13
申请人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikastsu Takaura
发明人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikastsu Takaura
IPC分类号： H01L27/24
CPC分类号： H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。
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28.发明授权公开(公告)号：US07195967B2
公开(公告)日：2007-03-27
申请号：US10701497
申请日：2003-11-06
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a channel region between the source/drain diffusion layers, impurities of the same conductivity type as the well are doped in an area apart from the diffusion regions. By using as a mask the gate formed in advance, tilted ion implantation in opposite directions is performed to form the diffusion layers and heavily impurity doped region of the same conductivity type as the well in a self-alignment manner relative to the gate.
摘要翻译： 在源极/漏极扩散层之间的沟道区域中，与扩散区域分开的区域掺杂与阱相同导电类型的杂质。 通过使用预先形成的栅极，执行相反方向的倾斜离子注入，以相对于栅极以自对准方式形成与阱相同导电类型的扩散层和重杂质掺杂区。
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公开(公告)号：US20060186463A1
公开(公告)日：2006-08-24
申请号：US11350118
申请日：2006-02-09
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115
摘要： The present invention enables to avoid a reduction in coupling ratio in a nonvolatile semiconductor memory device. The reduction is coupling ratio is caused due to difficulties in batch forming of a control gate material, an interpoly dielectric film material, and a floating gate material, the difficulties accompanying a reduction in word line width. Further, the invention enables to avoid damage caused in the batch forming on a gate oxide film. Before forming floating gates of memory cells of a nonvolatile memory, a space enclosed by insulating layers is formed for each of the floating gates of the memory cells, so that the floating gate is buried in the space. This structure is realized by processing the floating gates in a self alignment manner after depositing the floating gate material. Therefore, it is unnecessary to perform the batch forming of the control gate material, the interpoly dielectric film material, and the floating gate material in the case of processing the control gates, thereby ensuring adequate interpoly dielectric film capacitance.
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公开(公告)号：US09099177B2
公开(公告)日：2015-08-04
申请号：US14124725
申请日：2011-06-10
CPC分类号： G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/71 , G11C2213/75 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.
摘要翻译： 为了提供适合于小型化并允许接触电阻降低的半导体存储器件，存储器阵列（MA）的布线结构如下形成。 也就是说，字线（2）和位线（3）彼此并行扩展，每条字线与另一个字线捆绑，每个位线与另一个位线捆绑，并且两个位线 在相应的捆绑的两条字线上垂直形成的电路分离。 这样的配置使得可以：在电线的捆扎部分（MLC）处形成较大的接触; 并降低适于小型化的存储器阵列中的接触电阻。
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