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公开(公告)号：US20150084830A1
公开(公告)日：2015-03-26
申请号：US14038202
申请日：2013-09-26
Applicant: Adel Elsherbini , Telesphor Kamgaing
Inventor： Adel Elsherbini , Telesphor Kamgaing
CPC classification number: H01Q9/0414 , H01L2223/6677 , H01L2224/16227 , H01L2924/15321 , H01Q21/0006 , H01Q21/065 , H01Q21/067 , Y10T29/49016
Abstract: An antenna integrated in a package substrate, the antenna comprising an upper antenna element, a lower antenna element and a coupling element disposed between the upper antenna element and the lower antenna element, the coupling element comprising an aperture, and configured to provide a coupling between the upper antenna element and the lower antenna element.
Abstract translation: 集成在封装衬底中的天线，所述天线包括上天线元件，下天线元件和设置在所述上天线元件和所述下天线元件之间的耦合元件，所述耦合元件包括孔，并且被配置为提供 上天线元件和下天线元件。
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公开(公告)号：US20150069629A1
公开(公告)日：2015-03-12
申请号：US14543838
申请日：2014-11-17
Applicant: Chung Peng Jackson KONG , Chang-Tsung Fu , Telesphor Kamgaing , Chan Kim Lee , Ping Ping Ooi
Inventor： Chung Peng Jackson KONG , Chang-Tsung Fu , Telesphor Kamgaing , Chan Kim Lee , Ping Ping Ooi
IPC: H01L23/522 , H01L23/528
CPC classification number: H01L23/5226 , H01L23/49822 , H01L23/49827 , H01L23/528 , H01L2224/16
Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.
Abstract translation: 描述了采用多个互连级别以跨越封装长度传播或返回单条信号线的“混合”传输线路电路。 在封装传输线路电路实施例中，信号线在电耦合在一起的两个不同的互连级别中使用共同定位的迹线。 在另外的实施例中，参考平面被提供在至少一个共定位轨迹的上方，下方或共面上。 在实施例中，平衡信号线对包括作为传播信号线的两个相邻互连级别中的第一和第二同位置迹线，以及在两个相邻互连级别中的第三和第四同位序列作为具有接地平面Co 平面，和/或上方和/或下方两个相邻互连层。
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公开(公告)号：US08890302B2
公开(公告)日：2014-11-18
申请号：US13538887
申请日：2012-06-29
Applicant: Chung Peng (Jackson) Kong , Chang-Tsung Fu , Telesphor Kamgaing , Chan Kim Lee , Ping Ping Ooi
Inventor： Chung Peng (Jackson) Kong , Chang-Tsung Fu , Telesphor Kamgaing , Chan Kim Lee , Ping Ping Ooi
CPC classification number: H01L23/5226 , H01L23/49822 , H01L23/49827 , H01L23/528 , H01L2224/16
Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.
Abstract translation: 描述了采用多个互连级别以跨越封装长度传播或返回单条信号线的“混合”传输线路电路。 在封装传输线路电路实施例中，信号线在电耦合在一起的两个不同的互连级别中使用共同定位的迹线。 在另外的实施例中，参考平面被提供在至少一个共定位轨迹的上方，下方或共面上。 在实施例中，平衡信号线对包括作为传播信号线的两个相邻互连级别中的第一和第二同位置迹线，以及在两个相邻互连级别中的第三和第四同位序列作为具有接地平面Co 平面，和/或上方和/或下方两个相邻互连层。
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公开(公告)号：US08804366B2
公开(公告)日：2014-08-12
申请号：US13316811
申请日：2011-12-12
Applicant: Telesphor Kamgaing , Emile Davies-Venn
Inventor： Telesphor Kamgaing , Emile Davies-Venn
IPC: H05K7/00
CPC classification number: H01P1/212 , H01L2224/05553 , H01L2224/0603 , H01L2224/48095 , H01L2224/48225 , H01L2224/48237 , H01L2224/49113 , H01L2924/181 , H01L2924/00012
Abstract: A microelectronic package having a radio frequency (RF) amplifier circuit and, incorporating harmonic rejection filters and matching circuits integrally formed in the package is disclosed. A harmonic rejection filter may comprise a metal-insulator-metal (MIM) capacitor serially coupled between bond pads disposed on a RF amplifier circuit die, a first wire bond coupling a first bond pad to a package output, where the first bond pad is coupled to the output of the RF amplifier, and a second wire bond coupling a second bond pad to a package ground. The harmonic rejection filter may be appropriately configured to filter one or more harmonics at different frequencies.
Abstract translation: 公开了一种具有射频（RF）放大器电路并且并入谐波抑制滤波器和整体形成在封装中的匹配电路的微电子封装。 谐波抑制滤波器可以包括串联连接在RF放大器电路管芯上的接合焊盘之间的金属 - 绝缘体 - 金属（MIM）电容器，将第一接合焊盘耦合到封装输出端的第一引线键合，其中第一接合焊盘耦合 到RF放大器的输出，以及将第二接合焊盘耦合到封装地的第二引线接合。 谐波抑制滤波器可以被适当地配置为滤波不同频率的一个或多个谐波。
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公开(公告)号：US08710903B2
公开(公告)日：2014-04-29
申请号：US12217078
申请日：2008-06-30
Applicant: Bradley Oraw , Telesphor Kamgaing
Inventor： Bradley Oraw , Telesphor Kamgaing
IPC: G11C5/14
CPC classification number: G11C5/147 , H02M1/36 , H02M3/07 , H02M2003/072
Abstract: Drive and startup circuits are described particularly suitable for use with a switched capacitor divider. In one example, a drive circuit has a level shifter coupled to a gate of each switch of a switched capacitor drive circuit to couple alternating current into the respective gate, a positive phase low side driver coupled to each level shifter to drive the gates of the top switch path through the respective level shifters, and a negative phase low side driver coupled to each level shifter to drive gates of the bottom switch path through the respective level shifters. A startup circuit, such as a capacitive soft start circuit may be used to slow the application of the current to each switch.
Abstract translation: 驱动和启动电路被特别适用于开关电容分压器。 在一个示例中，驱动电路具有耦合到开关电容器驱动电路的每个开关的栅极的电平移位器，以将交流电耦合到相应的栅极中，耦合到每个电平移位器的正相低侧驱动器来驱动 通过相应电平移位器的顶部开关路径，以及耦合到每个电平移位器的负相位低侧驱动器，以驱动通过相应电平移位器的底部开关路径的栅极。 可以使用诸如电容软启动电路的启动电路来减慢对每个开关的电流的施加。
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Patent Agency Ranking
公开(公告)号：US20140027880A1
公开(公告)日：2014-01-30
申请号：US13976439
申请日：2011-12-29
Applicant: Andreas Duevel , Telesphor Kamgaing , Valluri R. Rao , Uwe Zillmann
Inventor： Andreas Duevel , Telesphor Kamgaing , Valluri R. Rao , Uwe Zillmann
IPC: H01L49/02
CPC classification number: H01L28/10 , H01F17/0006 , H01F2017/002 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L27/0688 , H01L27/08 , H01L2224/4813 , H01L2924/0002 , H01L2924/00012
Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.
Abstract translation: 使用导电贯穿体通孔在集成电路管芯中形成三维电感器，该穿通体通孔穿过管芯的主体并与管芯前侧上的一个或多个金属互连层接触并终止在管芯的背面 死。 在另一个实施例中，通孔通孔可以穿过设置在管芯主体中的插塞中的电介质材料。 另一方面，变压器可以通过耦合使用通孔通孔形成的多个电感器来形成。 在另一方面，三维电感器可以包括由片上金属化层的堆叠形成的导体和设置在金属化层之间的绝缘层中的导电贯通层通孔。 描述其他实施例。
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公开(公告)号：US20130058141A1
公开(公告)日：2013-03-07
申请号：US13664102
申请日：2012-10-30
Applicant: Bradley S. Oraw , Telesphor Kamgaing
Inventor： Bradley S. Oraw , Telesphor Kamgaing
CPC classification number: H02M3/07 , H02J1/102 , H02J9/005 , H02M2001/008 , Y10T307/406
Abstract: Series switches for power delivery. A regulator operated as a current source is arranged in parallel with a switched capacitor divider. A switched capacitor divider is configured in series with a plurality of linear regulators with each regulating one of a plurality of voltage outputs from the switched capacitor divider. In another embodiment, a series switch bridge has a first pair of switches connected in series with a second pair of switches across a voltage input, each switch within a pair of switches is switched in-phase with the other while the first pair of switches is switched out of phase with the second pair of switches. A balancing capacitor is coupled across one switch in both the first and second pair to be in parallel when either of the pair of switches is closed to reduce a charge imbalance between the switches.
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公开(公告)号：US20090322384A1
公开(公告)日：2009-12-31
申请号：US12217078
申请日：2008-06-30
Applicant: Bradley Oraw , Telesphor Kamgaing
Inventor： Bradley Oraw , Telesphor Kamgaing
IPC: G05F1/10
CPC classification number: G11C5/147 , H02M1/36 , H02M3/07 , H02M2003/072
Abstract: Drive and startup circuits are described particularly suitable for use with a switched capacitor divider. In one example, a drive circuit has a level shifter coupled to a gate of each switch of a switched capacitor drive circuit to couple alternating current into the respective gate, a positive phase low side driver coupled to each level shifter to drive the gates of the top switch path through the respective level shifters, and a negative phase low side driver coupled to each level shifter to drive gates of the bottom switch path through the respective level shifters. A startup circuit, such as a capacitive soft start circuit may be used to slow the application of the current to each switch.
Abstract translation: 驱动和启动电路被特别适用于开关电容分压器。 在一个示例中，驱动电路具有耦合到开关电容器驱动电路的每个开关的栅极的电平移位器，以将交流电耦合到相应的栅极中，耦合到每个电平移位器的正相低侧驱动器来驱动 通过相应电平移位器的顶部开关路径，以及耦合到每个电平移位器的负相位低侧驱动器，以驱动通过相应电平移位器的底部开关路径的栅极。 可以使用诸如电容软启动电路的启动电路来减慢对每个开关的电流的施加。
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公开(公告)号：US07548138B2
公开(公告)日：2009-06-16
申请号：US11240305
申请日：2005-09-29
Applicant: Telesphor Kamgaing
Inventor： Telesphor Kamgaing
IPC: H03H7/01
CPC classification number: H03H5/02 , H01F27/40 , H01F2017/0046 , H03H2001/0085
Abstract: A technique to provide a compact integration of inductor-capacitor resonator a capacitor having a top plate and a bottom plate embedding a dielectric layer. The top and bottom plates are substantially parallel to each other. An inductor having a first end is coupled to the capacitor at the bottom plate. The inductor has N turns surrounding the bottom plate in a spiral geometry. The inductor is co-planar to one of the top and bottom plates and ends at a second end.
Abstract translation: 一种提供电感器 - 电容谐振器紧凑集成的技术，其具有嵌入介电层的顶板和底板的电容器。 顶板和底板基本上彼此平行。 具有第一端的电感器在底板处耦合到电容器。 电感器以螺旋几何形式围绕底板N圈。 电感器与顶板和底板中的一个共面，并在第二端处终止。
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公开(公告)号：US20080238568A1
公开(公告)日：2008-10-02
申请号：US11729558
申请日：2007-03-29
Applicant: Emile Davies-venn , Telesphor Kamgaing
Inventor： Emile Davies-venn , Telesphor Kamgaing
IPC: H03H7/42
CPC classification number: H03H7/42 , H03H2001/0085 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/4602 , H05K2201/0187 , H05K2201/09509 , H05K2201/09536
Abstract: Methods and apparatus relating to package embedded three dimensional baluns are described. In one embodiment, components of one or more baluns may be embedded in a single semiconductor substrate. Other embodiments are also described.
Abstract translation: 描述了与封装嵌入式三维巴伦相关的方法和装置。 在一个实施例中，一个或多个巴伦的组件可以嵌入在单个半导体衬底中。 还描述了其它实施例。
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