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27 条记录 (耗时 0.019 秒)

    Terraced Film Stack
    22.
    发明申请
    Terraced Film Stack 有权
    梯田电影堆栈

    公开(公告)号：US20090072288A1

    公开(公告)日：2009-03-19

    申请号：US12274824

    申请日：2008-11-20

    申请人： Robert J. Hanson ,  Alex Schrinsky ,  Terry McDaniel

    发明人： Robert J. Hanson ,  Alex Schrinsky ,  Terry McDaniel

    IPC分类号： H01L27/06

    CPC分类号： H01L27/10894 ,  H01L21/76816 ,  H01L21/76843 ,  H01L27/10885

    摘要： A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure.

    摘要翻译： 公开了一种用于形成半导体器件（例如DRAM存储器件）的梯形膜堆叠的工艺和装置。 本发明解决了由薄膜堆叠中使用的不同蚀刻选择性的材料产生的蚀刻底切，如果不能解决，则可能导致器件故障。

    TERRACED FILM STACK
    23.
    发明申请
    TERRACED FILM STACK 有权
    TERRACED胶片堆叠

    公开(公告)号：US20070231995A1

    公开(公告)日：2007-10-04

    申请号：US11757594

    申请日：2007-06-04

    申请人： Robert Hanson ,  Alex Schrinsky ,  Terry McDaniel

    发明人： Robert Hanson ,  Alex Schrinsky ,  Terry McDaniel

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10894 ,  H01L21/76816 ,  H01L21/76843 ,  H01L27/10885

    摘要： A process directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure.

    摘要翻译： 公开了一种用于形成半导体器件（例如DRAM存储器件）的梯形膜叠层的工艺。 本发明解决了由薄膜堆叠中使用的不同蚀刻选择性的材料产生的蚀刻底切，如果不能解决，则可能导致器件故障。

    Systems and methods for forming additional metal routing in semiconductor devices
    24.
    发明申请
    Systems and methods for forming additional metal routing in semiconductor devices 有权
    用于在半导体器件中形成附加金属布线的系统和方法

    公开(公告)号：US20070164372A1

    公开(公告)日：2007-07-19

    申请号：US11331951

    申请日：2006-01-13

    申请人： Terry McDaniel ,  James Green ,  Mark Fischer

    发明人： Terry McDaniel ,  James Green ,  Mark Fischer

    IPC分类号： H01L29/76

    CPC分类号： H01L27/105 ,  H01L21/823475 ,  H01L21/823871 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11531 ,  H01L29/66545

    摘要： Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate regions of the memory device. As the size of semiconductor components decreases and circuit densities increase, the density of the metal routing in these upper metal layers becomes increasingly difficult to fabricate. By providing additional metal routing in the lower gate regions that may be coupled to the upper metal layers, the spacing requirements of the upper metal layers may be eased, while maintaining the size of the semiconductor device. In addition, the additional metal routing formed in the gate regions of the memory devices may be disposed parallel to other metal contacts in a strapping configuration, thus reducing a resistance of the metal contacts, such as buried digit lines of a DRAM memory cell.

    摘要翻译： 诸如DRAM存储器件的存储器件可以包括与存储器件的下部栅极区域接触的DRAM存储器的局部互连上方的一个或多个金属层。 随着半导体元件的尺寸减小和电路密度增加，这些上层金属层中的金属布线的密度越来越难于制造。 通过在可以耦合到上金属层的下栅极区域中提供额外的金属布线，可以在保持半导体器件的尺寸的同时，缓和上金属层的间隔要求。 此外，形成在存储器件的栅极区域中的附加金属布线可以以带状构造平行于其它金属触点设置，从而减小金属触点（例如DRAM存储单元的埋置数字线）的电阻。