公开(公告)号：US07553778B2

公开(公告)日：2009-06-30

申请号：US11356288

申请日：2006-02-17

申请人： Kazuyuki Sugahara ,  Naoki Nakagawa ,  Atsuhiro Sono ,  Shinsuke Yura ,  Kazushi Yamayoshi

发明人： Kazuyuki Sugahara ,  Naoki Nakagawa ,  Atsuhiro Sono ,  Shinsuke Yura ,  Kazushi Yamayoshi

IPC分类号： H01L21/00

CPC分类号： H01L21/02686 ,  H01L21/02422 ,  H01L21/02691 ,  H01L21/2026 ,  H01L27/1285 ,  H01L27/1296

摘要： A method for producing a semiconductor device includes irradiating an amorphous semiconductor film on an insulating material with a pulsed laser beam having a rectangular irradiation area, while scanning in a direction intersecting a longitudinal direction of the irradiation area, thereby forming a first polycrystalline semiconductor film, and irradiating a part of the amorphous semiconductor film with the laser beam, while scanning in a longitudinal direction intersecting the irradiation area, the part superposing the first polycrystalline semiconductor film and being adjacent to the first polycrystalline semiconductor film, thereby forming a second polycrystalline semiconductor film. The laser beam has a wavelength in a range from 390 nm to 640 nm, and the amorphous semiconductor film has a thickness in a range from 60 nm to 100 nm.

摘要翻译： 一种制造半导体器件的方法包括：在具有矩形照射区域的脉冲激光束的绝缘材料上照射非晶半导体膜，同时沿与照射区域的纵向相交的方向扫描，从而形成第一多晶半导体膜， 以及在与所述照射区域交叉的纵向方向上扫描所述非晶半导体膜的一部分，所述半导体膜与所述第一多晶半导体膜重叠，并且与所述第一多晶半导体膜相邻，从而形成第二多晶半导体膜 。 激光束的波长为390nm〜640nm，非晶半导体膜的厚度为60nm〜100nm。

公开(公告)号：US20060183304A1

公开(公告)日：2006-08-17

申请号：US11356288

申请日：2006-02-17

申请人： Kazuyuki Sugahara ,  Naoki Nakagawa ,  Atsuhiro Sono ,  Shinsuke Yura ,  Kazushi Yamayoshi

发明人： Kazuyuki Sugahara ,  Naoki Nakagawa ,  Atsuhiro Sono ,  Shinsuke Yura ,  Kazushi Yamayoshi

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02686 ,  H01L21/02422 ,  H01L21/02691 ,  H01L21/2026 ,  H01L27/1285 ,  H01L27/1296

摘要： A method for producing a semiconductor device includes irradiating an amorphous semiconductor film on an insulating material with a pulsed laser beam having a rectangular irradiation area, while scanning in a direction intersecting a longitudinal direction of the irradiation area, thereby forming a first polycrystalline semiconductor film, and irradiating a part of the amorphous semiconductor film with the laser beam, while scanning in a longitudinal direction intersecting the irradiation area, the part superposing the first polycrystalline semiconductor film and being adjacent to the first polycrystalline semiconductor film, thereby forming a second polycrystalline semiconductor film. The laser beam has a wavelength in a range from 390 nm to 640 nm, and the amorphous semiconductor film has a thickness in a range from 60 nm to 100 nm.

摘要翻译： 一种制造半导体器件的方法包括：在具有矩形照射区域的脉冲激光束的绝缘材料上照射非晶半导体膜，同时沿与照射区域的纵向相交的方向扫描，从而形成第一多晶半导体膜， 以及在与所述照射区域交叉的纵向方向上扫描所述非晶半导体膜的一部分，所述半导体膜与所述第一多晶半导体膜重叠，并且与所述第一多晶半导体膜相邻，从而形成第二多晶半导体膜 。 激光束的波长为390nm〜640nm，非晶半导体膜的厚度为60nm〜100nm。

公开(公告)号：US5514880A

公开(公告)日：1996-05-07

申请号：US142564

申请日：1993-10-28

申请人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

发明人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L27/11 ,  H01L27/1108 ,  H01L29/78654 ,  H01L27/1281 ,  Y10S257/903

摘要： In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

摘要翻译： 在TFT负载型的小型化的完全CMOS SRAM中，场效应薄膜晶体管（TFT）能够实现对存储单元的稳定的读/写操作并且可以降低其功耗。 形成在绝缘体上的场效应薄膜晶体管包括有源层和栅电极。 栅电极形成在有源层的沟道区上，其间具有栅极绝缘膜。 有源层由沟道区和源极/漏极区形成。 沟道区由单晶硅层形成，不包含晶界。 源/漏区由多晶硅层形成。 沟道区域的晶体缺陷密度小于109个/ cm 2。 薄膜晶体管的通道宽度为1μm，导通电流为0.25μA/μm，OFF电流为15fA /μm。 薄膜晶体管可以被施加到用作CMOS型SRAM的存储单元中的负载晶体管的p沟道MOS晶体管。

公开(公告)号：US5504376A

公开(公告)日：1996-04-02

申请号：US222502

申请日：1994-04-04

申请人： Kazuyuki Sugahara ,  Natsuo Ajika ,  Toshiaki Ogawa ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Kazuyuki Sugahara ,  Natsuo Ajika ,  Toshiaki Ogawa ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L27/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/822 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L21/2007 ,  H01L21/76251 ,  H01L21/8221 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

摘要： In a method of manufacturing a stacked-type semiconductor device, firstly, a first semiconductor substrate having a first device formed thereon is covered with an interlayer insulating layer and a planarized polycrystalline silicon layer is formed on the interlayer insulating layer. The first semiconductor substrate and a second semiconductor substrate are joined together by putting the surface of the polycrystalline silicon layer in close contact with the surface of a refractory metal layer formed on the second semiconductor substrate, applying thermal treatment at 700.degree. C. or below and changing the refractory metal layer to silicide.

摘要翻译： 在叠层型半导体器件的制造方法中，首先，在层间绝缘层上形成有具有形成在其上的第一器件的第一半导体衬底，层间绝缘层形成平坦化的多晶硅层。 将第一半导体衬底和第二半导体衬底通过将多晶硅层的表面与形成在第二半导体衬底上的难熔金属层的表面紧密接触，在700℃以下进行热处理， 将难熔金属层改为硅化物。

公开(公告)号：US5413968A

公开(公告)日：1995-05-09

申请号：US22876

申请日：1993-02-25

申请人： Yasuo Inoue ,  Kazuyuki Sugahara ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Yasuo Inoue ,  Kazuyuki Sugahara ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L21/3205 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L27/11 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L23/485 ,  H01L27/11 ,  H01L27/1112 ,  H01L2924/0002

摘要： A semiconductor device includes a conductor layer (3, 7) having a silicon crystal, an insulator layer (5, 15) formed on the surface of the conductor layer (3, 7) having a contact hole therethrough to said surface of the conductor layer (3, 7), an interconnecting portion formed at a predetermined location in the insulator layer (5, 15) and having a contact hole (6, 9) the bottom surface of which becomes the surface of the conductor layer (3, 7), a barrier layer (14) formed at the bottom of said contact hole at least on the surface of the conductor layer (3, 7) in the interconnecting portion, and a metal silicide layer (12) formed on the barrier layer (14). This semiconductor device is manufactured by depositing the insulator layer (5, 15) having the contact hole (6, 9) on the conductor layer (3, 7) having the silicon crystal, forming the barrier layer (14) and the polysilicon layer (7, 10) overlapping each other in the contact hole (6, 9) and on the insulator layer (5, 15) and then patterning these overlapping barrier layer (14) and polysilicon layer (7, 10), forming a metal layer (8, 11) thereon to be silicidized, and removing unreacted metal. The semiconductor device thus manufactured prevents a suction of silicon from the conductor layer (3, 7) to the metal silicide layer (12) and hence prevents an increase in resistance value due to a deficiency of silicon produced in the conductor layer (3, 7), thereby minimizing a series resistance of the metal silicide layer (12), a contact portion and the conductor layer (3, 7).

摘要翻译： 半导体器件包括具有硅晶体的导体层（3,7），形成在导体层（3,7）的表面上的绝缘体层（5,15），其具有穿过其的导体层的所述表面的接触孔 （3,7），形成在所述绝缘体层（5,15）中的预定位置处并具有其底表面成为所述导体层（3,7）的表面的接触孔（6,9）的互连部分， 至少在所述互连部分中的所述导体层（3,7）的表面上形成在所述接触孔的底部处的阻挡层（14）和形成在所述阻挡层（14）上的金属硅化物层（12） 。 该半导体器件通过在具有硅晶体的导体层（3,7）上沉积具有接触孔（6,9）的绝缘体层（5,15），形成阻挡层（14）和多晶硅层（ 7,10）在接触孔（6,9）和绝缘体层（5,15）上彼此重叠，然后对这些重叠的阻挡层（14）和多晶硅层（7,10）进行构图，形成金属层 8,11）在其上被硅化，并除去未反应的金属。 这样制造的半导体器件防止硅从导体层（3,7）吸收到金属硅化物层（12），从而防止由于导体层（3,7）中产生的硅的缺陷导致的电阻值增加 ），从而使金属硅化物层（12），接触部分和导体层（3,7）的串联电阻最小化。

公开(公告)号：US5094714A

公开(公告)日：1992-03-10

申请号：US607800

申请日：1990-10-31

申请人： Tadashi Nishimura ,  Kazuyuki Sugahara ,  Shigeru Kusunoki ,  Yasuo Inoue

发明人： Tadashi Nishimura ,  Kazuyuki Sugahara ,  Shigeru Kusunoki ,  Yasuo Inoue

IPC分类号： H01L21/20 ,  C30B13/00 ,  H01L21/762

CPC分类号： C30B29/06 ,  C30B13/00 ,  H01L21/76297 ,  Y10T428/31504

摘要： A wafer structure for forming a semiconductor single crystal film comprises a semiconductor single crystal substrate, a plurality of recesses formed in a grooved shape to one main surface of the semiconductor single crystal substrate, insulation material embedded to the inside of these recesses, an insulation layer deposited over the insulation material and the semiconductor single crystal substrate and integrated with the insulation material and a polycrystalline or amorphous semiconductor layer to be recrystallized disposed over the insulation layer.A wafer structure with no or less grain boundaries can be obtained. Further, polycrystalline or amorphous semiconductor layer can be prevented from peeling off the substrate by the additional layering of a protecting insulation layer.

摘要翻译： 用于形成半导体单晶膜的晶片结构包括半导体单晶衬底，形成为半导体单晶衬底的一个主表面的沟槽形状的多个凹槽，嵌入到这些凹部内部的绝缘材料，绝缘层 沉积在绝缘材料和半导体单晶衬底上并与绝缘材料一体化，并且将多晶或非晶半导体层重结晶设置在绝缘层上。 可以获得没有或没有晶界的晶片结构。 此外，通过附加的保护绝缘层的分层，可以防止多晶或非晶半导体层从基板上剥离。

公开(公告)号：US5006913A

公开(公告)日：1991-04-09

申请号：US430402

申请日：1989-11-02

申请人： Kazuyuki Sugahara ,  Shigeru Kusunoki ,  Takashi Ipposhi

发明人： Kazuyuki Sugahara ,  Shigeru Kusunoki ,  Takashi Ipposhi

IPC分类号： H01L21/822 ,  H01L27/06

CPC分类号： H01L21/8221 ,  H01L27/0688

摘要： A field effect transistor is formed as a first semiconductor element on a main surface of a first semiconductor layer (1). An interlayer insulating film (10) constituted by a first insulating layer (101) and a second insulating layer (102) is formed on the first semiconductor element. The first insulating layer (101) is formed of a BPSG film having a glass transition point no higher than 750.degree. C. The second insulating layer (102) is formed of a silicon oxide film having a glass transition point higher than 750.degree. C. and a thickness no less than 2000 .ANG. and no more than 1 .mu.m formed on the first insulating layer (101). A second semiconductor layer (11) is formed on the second insulating layer (102) of the interlayer insulating film (10). The second semiconductor layer (11) is formed to be an island, with the peripheral portions isolated. A field effect transistor as a second semiconductor element is formed in the second semiconductor layer (11). The first insulating layer (101) suppresses stress remained in the second semiconductor layer (11) derived from a difference between coefficient of thermal expansion of the second semiconductor layer (11) and the interlayer insulating film (10). The second insulating layer (102) suppresses lateral distortion generated in the semiconductor layer (11). The characteristics of the second semiconductor element can be improved.

摘要翻译： 在第一半导体层（1）的主表面上形成场效应晶体管作为第一半导体元件。 在第一半导体元件上形成由第一绝缘层（101）和第二绝缘层（102）构成的层间绝缘膜（10）。 第一绝缘层（101）由玻璃化转变点不高于750℃的BPSG膜形成。第二绝缘层（102）由玻璃化转变点高于750℃的氧化硅膜形成。 并且在第一绝缘层（101）上形成的厚度不小于2000，不大于1μm。 在层间绝缘膜（10）的第二绝缘层（102）上形成第二半导体层（11）。 第二半导体层（11）形成为岛状，其外围部分被隔离。 在第二半导体层（11）中形成作为第二半导体元件的场效应晶体管。 第一绝缘层（101）抑制由第二半导体层（11）和层间绝缘膜（10）之间的热膨胀系数之差导出的第二半导体层（11）中残留的应力。 第二绝缘层（102）抑制在半导体层（11）中产生的横向失真。 可以提高第二半导体元件的特性。

公开(公告)号：US4953125A

公开(公告)日：1990-08-28

申请号：US173749

申请日：1988-03-25

申请人： Yoshinori Okumura ,  Akihiko Ohsaki ,  Kazuyuki Sugahara ,  Tatsuhiko Ikeda

发明人： Yoshinori Okumura ,  Akihiko Ohsaki ,  Kazuyuki Sugahara ,  Tatsuhiko Ikeda

IPC分类号： H01L29/41 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10829

摘要： A semiconductor memory device includes a first trench serving as a memory cell formed in a p type semiconductor substrate, a first n type semiconductor region formed adjacent to the trench region and on the major surface of the semiconductor substrate, a conductive layer serving as an electron active region formed adjacent to the first n type region and on the major surface of the semiconductor substrate, a second n type semiconductor region formed adjacent to the electron active region and on the major surface of the semiconductor substrate, a second trench formed adjacent to the second n type semiconductor region in the major surface of the semiconductor substrate which is shallower than the first trench, an interconnection layer serving as a bit line formed in a self-aligning manner in the sidewall portion of the second trench which is shallower than the first trench and a gate electrode serving as a word line formed in the upper portion of the conductive layer through an oxide film.

摘要翻译： 半导体存储器件包括用作形成在p型半导体衬底中的存储单元的第一沟槽，与沟槽区相邻并且在半导体衬底的主表面上形成的第一n型半导体区，用作电子活性的导电层 形成在与第一n型区域相邻并且在半导体衬底的主表面上形成的第二n型半导体区域，形成在与电子有源区相邻并且在半导体衬底的主表面上，第二沟槽， 在半导体衬底的主表面上比第一沟槽浅的n型半导体区域，在第二沟槽的侧壁部分中以自对准的方式形成的位线的互连层比第一沟槽浅 以及用作通过氧化膜形成在导电层的上部的字线的栅电极 。

公开(公告)号：US4845537A

公开(公告)日：1989-07-04

申请号：US127138

申请日：1987-12-01

申请人： Tadashi Nishimura ,  Kazuyuki Sugahara ,  Shigeru Kusunoki ,  Akihiko Ohsaki

发明人： Tadashi Nishimura ,  Kazuyuki Sugahara ,  Shigeru Kusunoki ,  Akihiko Ohsaki

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10841 ,  H01L29/7827

摘要： A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs. 0O048455372

摘要翻译： 一种垂直MOS晶体管，其沟道长度由设置在半导体衬底上的绝缘层的厚度确定，而不是由形成晶体管的沟槽的深度确定。 结果，晶体管的特性相对不受在形成期间进行的掺杂和热处理步骤的影响。 此外，晶体管可以形成为占据非常小的表面积，使其适用于高密度DRAM。 0048455372

公开(公告)号：US4822752A

公开(公告)日：1989-04-18

申请号：US022717

申请日：1987-03-06

申请人： Kazuyuki Sugahara ,  Tadashi Nishimura ,  Shigeru Kusunoki ,  Yasuo Inoue

发明人： Kazuyuki Sugahara ,  Tadashi Nishimura ,  Shigeru Kusunoki ,  Yasuo Inoue

IPC分类号： H01L21/20 ,  H01L21/268 ,  H01L21/822 ,  H01L29/04 ,  H01L21/306 ,  H01L21/326 ,  H01L21/479

CPC分类号： H01L21/8221 ,  H01L21/2026 ,  H01L21/268 ,  H01L29/045 ,  Y10S117/904 ,  Y10S148/09 ,  Y10S148/091 ,  Y10S148/093

摘要： Disclosed herein is a process for producing a single crystal layer of a semiconductor device, which comprises the steps of providing an oxide insulator layer separated by an opening part for seeding, on a major surface of a single crystal semiconductor substrate of the cubic system, providing a polycrystalline or amorphous semiconductor layer on the entire surface of the insulator layer inclusive of the opening part, then providing a protective layer comprising at least a reflective or anti-reflection film comprising strips of a predetermined width, in a predetermined direction relative to the opening part and at a predetermined interval, the protective layer capable of controlling the temperature distributions in the semiconductor layer at the parts corresponding to the stripes or the parts not corresponding to the stripes, thereby completing a base for producing a semiconductor device, thereafter the surface of the base is irradiated with an energy beam through the striped reflective or anti-reflection film to melt the polycrystalline or amorphous semiconductor and scanning the energy beam in a predetermined direction such that the direction of the crystal of the semiconductor re-solidified and converted into a single crystal accords with a {111} plane, to produce the single crystal of the semiconductor device. Also disclosed is a semiconductor device produced by the method, which comprises a single crystal layer having a wide range of a crystal in a predetermined direction relative to the facial orientation of the major surface of the substrate, and has a three-dimensional semiconductor circuit element construction.

摘要翻译： 本发明公开了一种制造半导体器件的单晶层的方法，其包括以下步骤：在立方晶系的单晶半导体衬底的主表面上提供由用于接种的开口部分开的氧化物绝缘体层，提供 在包括开口部分的绝缘体层的整个表面上的多晶或非晶半导体层，然后提供保护层，该保护层至少包括反射膜或防反射膜，该反射膜或抗反射膜包括相对于开口的预定方向的预定宽度的条 部分并且以预定间隔，保护层能够控制对应于条纹的部分或不对应于条纹的部分的半导体层中的温度分布，从而完成用于制造半导体器件的基底，之后， 用能量束通过条纹反射照射基座 或抗反射膜，以熔化多晶或非晶半导体并沿预定方向扫描能量束，使得半导体晶体的方向重新固化并转换成单晶符合{111}面，以产生 半导体器件的单晶。 还公开了一种通过该方法制造的半导体器件，该半导体器件包括相对于衬底的主表面的面取向在预定方向上具有宽范围的晶体的单晶层，并且具有三维半导体电路元件 施工。