公开(公告)号：US20070232033A1

公开(公告)日：2007-10-04

申请号：US11562445

申请日：2006-11-22

申请人： Karsten Wieczorek ,  Thorsten Kammler ,  Thomas Feudel ,  Martin Gerhardt

发明人： Karsten Wieczorek ,  Thorsten Kammler ,  Thomas Feudel ,  Martin Gerhardt

IPC分类号： H01L21/36

CPC分类号： H01L21/02667 ,  H01L21/2022 ,  H01L21/2026 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： By using a combination of solid phase epitaxy re-growth and laser annealing, the present invention provides a low thermal budget method which allows the crystal lattice of a semiconductor surface to recover after the doping by ion implantation. The low thermal budget limits the out-diffusion of the dopants ions, thus avoiding the enlargement of the doped source/drain regions. Therefore, the method is suited, for instance, for the fabrication of ultra-shallow source/drain regions in MOS transistors elements. The method according to the present invention comprises a first pre-amorphization process in order to limit channeling effects, a doping process by ion implantation and a re-crystallization by solid phase epitaxy, followed by laser annealing.

摘要翻译： 通过使用固相外延再生长和激光退火的组合，本发明提供了一种低热预算方法，其允许半导体表面的晶格在通过离子注入进行掺杂之后恢复。 低热预算限制了掺杂剂离子的扩散，从而避免了掺杂源极/漏极区的扩大。 因此，该方法适用于例如在MOS晶体管元件中制造超浅源极/漏极区域。 根据本发明的方法包括第一预非晶化过程以限制沟道效应，通过离子注入的掺杂过程和通过固相外延的重结晶，随后进行激光退火。

公开(公告)号：US20090035924A1

公开(公告)日：2009-02-05

申请号：US12037533

申请日：2008-02-26

申请人： Thomas Feudel ,  Manfred Horstmann ,  Andreas Gehring

发明人： Thomas Feudel ,  Manfred Horstmann ,  Andreas Gehring

IPC分类号： H01L21/265

CPC分类号： H01L21/823418 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/82345 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a semiconductor structure includes providing a substrate having a first feature and a second feature. A mask is formed over the substrate. The mask covers the first feature. An ion implantation process is performed to introduce ions of a non-doping element into the second feature. The mask is adapted to absorb ions impinging on the first feature. After the ion implantation process, an annealing process is performed.

摘要翻译： 形成半导体结构的方法包括提供具有第一特征和第二特征的基板。 在衬底上形成掩模。 面罩涵盖了第一个功能。 执行离子注入工艺以将非掺杂元素的离子引入到第二特征中。 掩模适于吸收撞击第一特征的离子。 在离子注入工艺之后，进行退火处理。

公开(公告)号：US06846708B2

公开(公告)日：2005-01-25

申请号：US10601717

申请日：2003-06-23

申请人： Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

发明人： Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586

摘要： An implanting process for amorphizing a crystalline substrate is proposed according to the present invention. In particular, according to the present invention, amorphous regions are formed in a substrate by exposing the substrate to an ion beam which is kept at a tilt angle between 10 and 80 degrees with respect to the surface of the substrate. Accordingly, ion channeling during subsequent implanting processes is prevented not only in the vertical direction but also in the horizontal direction so that doped regions exhibiting optimum doping profile tailoring may be realized.

摘要翻译： 根据本发明提出了一种用于非晶化晶体衬底的注入工艺。 特别地，根据本发明，通过将衬底暴露于相对于衬底的表面保持在10至80度之间的倾斜角的离子束，在衬底中形成非晶区域。 因此，不仅在垂直方向上而且在水平方向上都防止后续植入过程中的离子通道化，从而可以实现具有最佳掺杂分布调整的掺杂区域。

公开(公告)号：US06822430B2

公开(公告)日：2004-11-23

申请号：US10602577

申请日：2003-06-24

申请人： Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

发明人： Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

IPC分类号： G01N2700

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G06F17/5018 ,  H01L22/34

摘要： A cost-efficient and reliable method for assessing lateral dopant profiles includes the estimation of a reference profile formed below a gate structure of a transistor device. The overlap capacitance is then determined for at least two different overlaps, created by different spacer widths, and the lateral extension of a dopant profile to be measured, is estimated on the basis of a relationship between overlap capacitance and spacer width for the reference dopant profile.

摘要翻译： 用于评估横向掺杂物分布的成本有效且可靠的方法包括在晶体管器件的栅极结构之下形成的参考分布的估计。 然后基于重叠电容和参考掺杂物分布的间隔物宽度之间的关系来估计重叠电容对于由不同的间隔物宽度产生的至少两个不同的重叠，并且待测量的掺杂物分布的横向延伸。 。

公开(公告)号：US06593175B2

公开(公告)日：2003-07-15

申请号：US09809710

申请日：2001-03-14

申请人： Thomas Feudel ,  Manfred Horstmann ,  Christian Krüger

发明人： Thomas Feudel ,  Manfred Horstmann ,  Christian Krüger

IPC分类号： H01L2100

CPC分类号： H01L21/28211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/31658 ,  H01L21/32 ,  H01L27/1203 ,  H01L29/42368

摘要： A method of forming an oxide layer on a substrate comprises deposition of a mask layer with an opening for defining the area where the oxide layer is to be formed, and an ion implantation step performed with a tilt angle so as to obtain a varying ion concentration. In a subsequent single oxidation step, an oxide layer is formed having a thickness that varies in conformity with the ion concentration. This method may advantageously be applied to the formation of a gate insulation layer in a field effect transistor.

公开(公告)号：US20080268625A1

公开(公告)日：2008-10-30

申请号：US12023743

申请日：2008-01-31

申请人： Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

发明人： Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

IPC分类号： H01L21/425

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848

摘要： By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.

摘要翻译： 通过组合用于调节有效沟道长度的退火工艺和在深漏极和源极注入之后执行的基本上无扩散的退火工艺，可以基本上增加漏极和源极区域的垂直延伸，而不影响先前调节的沟道长度。 以这种方式，在SOI器件中，漏极和源极区域可以向下延伸到掩埋绝缘层，从而减小寄生电容，同时可以改善延伸区域中的掺杂剂激活程度和因此的串联电阻。 此外，在用于调整沟道长度的退火工艺期间较不重要的工艺参数可以为降低晶体管器件的横向尺寸提供潜力。

公开(公告)号：US07208397B2

公开(公告)日：2007-04-24

申请号：US11122740

申请日：2005-05-05

申请人： Thomas Feudel ,  Manfred Horstmann ,  Markus Lenski

发明人： Thomas Feudel ,  Manfred Horstmann ,  Markus Lenski

IPC分类号： H01L21/425 ,  H01L21/22

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/66659 ,  H01L29/7835

摘要： By providing an asymmetric design of a halo region and extension regions of a field effect transistor, the transistor performance may significantly be enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even completely be avoided, wherein a moderately reduced concentration gradient may further enhance the transistor performance.

摘要翻译： 通过提供场效应晶体管的光晕区域和延伸区域的非对称设计，对于给定的基本晶体管架构，晶体管性能可以显着增强。 特别地，由于提供了卤素区域，可能在源极侧产生具有PN结的陡峭浓度梯度的大的重叠区域，而可以显着地减少或甚至可以完全避免漏极重叠，其中适度地 降低的浓度梯度可进一步提高晶体管的性能。

公开(公告)号：US06905924B2

公开(公告)日：2005-06-14

申请号：US10629436

申请日：2003-07-29

申请人： Gert Burbach ,  Manfred Horstmann ,  Thomas Feudel

发明人： Gert Burbach ,  Manfred Horstmann ,  Thomas Feudel

IPC分类号： H01L29/861 ,  H01L29/868 ,  H01L21/8234

CPC分类号： H01L29/868 ,  H01L29/861

摘要： In an SOI diode structure, the conventional transistor-like MOS configuration is eliminated by replacing the polysilicon line by a completely dielectric region. This region may be used as an implantation mask to control a dopant gradient of a PN-junction that forms below the dielectric region. Moreover, during the salicide process, the dielectric region prevents the PN-junction from being shorted. Thus, a depletion of the active region caused by the MOS structure may be avoided. Therefore, the functioning of the PN-junction is maintained even for extremely thin semiconductor layers.

摘要翻译： 在SOI二极管结构中，通过将多晶硅线替换为完全介电区域来消除传统的晶体管状MOS结构。 该区域可以用作注入掩模以控制形成在电介质区域之下的PN结的掺杂剂梯度。 此外，在自对准硅化物工艺期间，电介质区域防止PN结短路。 因此，可以避免由MOS结构引起的有源区的耗尽。 因此，即使对于极薄的半导体层也保持PN结的功能。

公开(公告)号：US08623742B2

公开(公告)日：2014-01-07

申请号：US13079341

申请日：2011-04-04

申请人： Stephan Kronholz ,  Matthias Kessler ,  Thomas Feudel

发明人： Stephan Kronholz ,  Matthias Kessler ,  Thomas Feudel

IPC分类号： H01L21/76

CPC分类号： H01L29/78621 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7848

摘要： A reduction in material loss of trench isolation structures prior to forming a strain-inducing semiconductor alloy in transistor elements may result in superior device uniformity, for instance with respect to drive current and threshold voltage. To this end, at least one etch process using diluted hydrofluoric acid may be omitted when forming the shallow trench isolations, while at the same time providing a high degree of compatibility with conventional process strategies.

摘要翻译： 在晶体管元件中形成应变诱导半导体合金之前，沟槽隔离结构的材料损耗的减少可以导致例如相对于驱动电流和阈值电压的优异的器件均匀性。 为此，当形成浅沟槽隔离时，可以省略使用稀释氢氟酸的至少一个蚀刻工艺，同时提供与常规工艺策略的高度兼容性。

公开(公告)号：US20110121398A1

公开(公告)日：2011-05-26

申请号：US12623683

申请日：2009-11-23

申请人： Jan Hoentschel ,  Thomas Feudel ,  Ralf Illgen

发明人： Jan Hoentschel ,  Thomas Feudel ,  Ralf Illgen

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/324 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848

摘要： During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained in the adjacent channel region.

摘要翻译： 在制造高级晶体管期间，通过在完成基本晶体管配置之后执行毫秒退火处理可以抑制显着的掺杂剂扩散，其中还可以通过在侧壁间隔结构内形成应变诱导区域来获得应力记忆技术。 由于在间隔结构中形成相应的空隙，所以可以在相邻沟道区域获得高拉伸应变分量。