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175 条记录 (耗时 0.025 秒)

    Systems and methods for offset cancellation in integrated transceivers
    22.
    发明授权
    Systems and methods for offset cancellation in integrated transceivers 有权
    集成收发器偏移消除的系统和方法

    公开(公告)号：US07586983B1

    公开(公告)日：2009-09-08

    申请号：US11510446

    申请日：2006-08-24

    申请人： Sergey Shumarayev ,  Wilson Wong ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Sergey Shumarayev ,  Wilson Wong ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H03K5/159 ,  H04B1/10

    CPC分类号： H04L25/03057

    摘要： In high speed receiver circuitry (e.g., on a programmable logic device (PLD) or the like), decision feedback equalization (DFE) circuitry is used to at least partly cancel unwanted offset (e.g., from other elements of the receiver). The data input to the receiver is tristated; and then each DFE tap coefficient is varied in turn to find coefficient values that are associated with transitions between oscillation and non-oscillation of the receiver output signal. The coefficient values found in this way are used to select trial values. If the output signal of the receiver does not oscillate when these trial values are used, the process is repeated starting from these (or subsequent) trial values until a final set of trial values does allow oscillation of the receiver output signal.

    摘要翻译： 在高速接收机电路（例如，在可编程逻辑器件（PLD）等上）中，使用判决反馈均衡（DFE）电路来至少部分地消除不期望的偏移（例如，从接收机的其他元件）。 输入到接收机的数据被三态化; 然后依次改变每个DFE抽头系数，以找到与接收机输出信号的振荡和非振荡之间的转换相关联的系数值。 以这种方式找到的系数值用于选择试验值。 如果接收机的输出信号在使用这些试验值时不振荡，则从这些（或后续）试验值开始重复该过程，直到最终的试验值确定允许接收器输出信号的振荡。

    Variable-bandwidth loop filter methods and apparatus
    24.
    发明授权
    Variable-bandwidth loop filter methods and apparatus 失效
    可变带宽环路滤波器的方法和装置

    公开(公告)号：US07436228B1

    公开(公告)日：2008-10-14

    申请号：US11317126

    申请日：2005-12-22

    申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong

    发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong

    IPC分类号： H03K5/00 ,  H03L7/06

    CPC分类号： H03L7/087 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/18

    摘要： Methods and apparatus are provided for varying the bandwidth of a loop filter in a loop circuit (e.g., a phase-locked loop circuit). The loop filter can include first and second resistor circuitries coupled to a capacitor. One of the resistor circuitries can be coupled to an output of the loop circuit in response to selection of a mode of operation. The resistor circuitries can each include a plurality of resistors that can be selectively coupled in series to the capacitor or bypassed. In addition, the output of the loop circuit can be coupled to a second capacitor. Either or both of the capacitors can be programmable.

    摘要翻译： 提供了用于改变环路电路（例如，锁相环电路）中的环路滤波器的带宽的方法和装置。 环路滤波器可以包括耦合到电容器的第一和第二电阻器电路。 响应于操作模式的选择，电阻器电路中的一个可以耦合到环路电路的输出。 电阻器电路可以各自包括可以选择性地串联耦合到电容器或绕过的多个电阻器。 此外，环路电路的输出可以耦合到第二电容器。 电容器中的任一个或两个可以是可编程的。

    Techniques for Reducing Duty Cycle Distortion in Periodic Signals
    26.
    发明申请
    Techniques for Reducing Duty Cycle Distortion in Periodic Signals 有权
    降低周期信号占空比变形的技术

    公开(公告)号：US20120256670A1

    公开(公告)日：2012-10-11

    申请号：US13083431

    申请日：2011-04-08

    申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

    发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  H03K3/017 ,  H03K5/12 ,  H03M9/00

    摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

    摘要翻译： 发射机电路可操作以响应于第一周期性信号提供输出信号。 多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。 多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。 采样器电路可操作以在第一操作阶段产生所选信号的第一采样。 采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。 占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

    Techniques for generating fractional clock signals
    28.
    发明授权
    Techniques for generating fractional clock signals 有权
    产生分数时钟信号的技术

    公开(公告)号：US07956696B2

    公开(公告)日：2011-06-07

    申请号：US12234114

    申请日：2008-09-19

    申请人： Tim Tri Hoang ,  Wilson Wong ,  Sergey Shumarayev

    发明人： Tim Tri Hoang ,  Wilson Wong ,  Sergey Shumarayev

    IPC分类号： H03L7/085 ,  H03B19/00

    CPC分类号： H03L7/099 ,  H03L7/18

    摘要： A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.

    摘要翻译： 电路包括相位检测电路，时钟信号发生电路，第一分频器和第二分频器。 相位检测电路将输入时钟信号与反馈信号进行比较以产生控制信号。 时钟信号产生电路响应于控制信号产生周期性输出信号。 第一分频器将周期性输出信号的频率除以第一值，以产生第一分频信号。 第二分频器将周期性输出信号的频率除以第二值，以产生第二分频信号。 在不同的时间间隔期间，第一和第二分频信号作为反馈信号被路由到相位检测电路。

    Signal detect for high-speed serial interface
    29.
    发明授权
    Signal detect for high-speed serial interface 有权
    信号检测用于高速串行接口

    公开(公告)号：US07899649B1

    公开(公告)日：2011-03-01

    申请号：US12053884

    申请日：2008-03-24

    申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

    发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

    IPC分类号： G06F19/00

    CPC分类号： H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

    摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

    摘要翻译： 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

    Clock distribution techniques for channels
    30.
    发明授权
    Clock distribution techniques for channels 有权
    频道的时钟分配技术

    公开(公告)号：US07791370B1

    公开(公告)日：2010-09-07

    申请号：US12470455

    申请日：2009-05-21

    申请人： Tim Tri Hoang ,  Thungoc M. Tran ,  Wilson Wong ,  Sergey Shumarayev

    发明人： Tim Tri Hoang ,  Thungoc M. Tran ,  Wilson Wong ,  Sergey Shumarayev

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： G06F1/10

    摘要： A circuit includes a first area, a second area, and a third area. The second area includes a locked loop circuit that generates a clock signal. The locked loop circuit receives a supply voltage that is isolated from noise generated in the first area. The third area includes multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads. The third area is separate from the second area in the circuit.

    摘要翻译： 电路包括第一区域，第二区域和第三区域。 第二区域包括产生时钟信号的锁定环路电路。 锁定环电路接收与第一区域中产生的噪声隔离的电源电压。 第三区域包括多个通道的四通道，并且时钟线耦合以将在第二区域中产生的至少一个时钟信号路由到每个四通道中的通道。 第三个区域与电路中的第二个区域分开。