公开(公告)号：US06214680B1

公开(公告)日：2001-04-10

申请号：US09460111

申请日：1999-12-13

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ink Ong ,  Sang Yee Loong

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ink Ong ,  Sang Yee Loong

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545

摘要： A new method of fabricating a MOSFET device is described. A semiconductor substrate is provided and isolation areas are formed isolating active areas in the substrate. An oxide layer is provided overlying both the substrate and isolation area and is patterned and etched to expose two areas within an isolated active area of the substrate. Selective epitaxial growth (SEG) using intrinsic silicon is performed to fill the exposed substrate areas formed in the previous etch step. The oxide layer region in the active area between the two epitaxially grown silicon regions is then etched, exposing the substrate. This is followed by a gate oxide growth and a polysilicon deposition. Planarization is then performed on the surface to expose the two epitaxially grown silicon regions. A second oxide is grown consuming some of the polysilicon gate and the epitaxially grown silicon. This consumption occurs at a higher rate at the upper surface and thus shapes the gate and epitaxially grown silicon into trapezoids with the base being wider than the top. The oxide is then etched leaving V-shaped trenches between the polysilicon and epitaxially grown silicon. A low-angle implantation is performed creating the source/drain extensions in the substrate below the V-shaped trenches. A third oxide is deposited filling the V-shaped groove and overlying the surface of the wafer. A second planarization is performed exposing the top of the epitaxially grown silicon regions and the polysilicon gate. A second implantation is performed to dope the polysilicon gate and epitaxially grown silicon regions. The doped portions of the epitaxially grown silicon form the source drain electrodes of the MOSFET. This is then followed by a salicidation step for metalization and annealing of the second implantation completing the MOSFET device.

摘要翻译： 描述了一种制造MOSFET器件的新方法。 提供半导体衬底，并且形成隔离区域以隔离衬底中的有源区域。 提供覆盖衬底和隔离区域的氧化物层，并且被图案化和蚀刻以暴露衬底的隔离有效区域内的两个区域。 执行使用本征硅的选择性外延生长（SEG）以填充在先前蚀刻步骤中形成的暴露的衬底区域。 然后蚀刻两个外延生长的硅区域之间的有源区域中的氧化物层区域，暴露衬底。 之后是栅极氧化物生长和多晶硅沉积。 然后在表面上进行平面化以暴露两个外延生长的硅区域。 第二氧化物生长消耗一些多晶硅栅极和外延生长的硅。 这种消耗以较高的速率发生在上表面，因此将浇口和外延生长的硅形成为梯形，基部比顶部宽。 然后蚀刻氧化物，留下多晶硅和外延生长的硅之间的V形沟槽。 执行低角度注入，在V形沟槽下面的衬底中产生源极/漏极延伸部。 沉积填充V形槽并覆盖晶片表面的第三氧化物。 进行外延生长的硅区域和多晶硅栅极的顶部的第二平面化。 进行第二次注入以掺杂多晶硅栅极和外延生长的硅区域。 外延生长硅的掺杂部分形成MOSFET的源极漏极。 然后进行用于金属化和退火完成MOSFET器件的第二次注入的盐析步骤。

公开(公告)号：US06803314B2

公开(公告)日：2004-10-12

申请号：US09845480

申请日：2001-04-30

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Yee Chong Wong ,  Sang Yee Long

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Yee Chong Wong ,  Sang Yee Long

IPC分类号： H01L21302

CPC分类号： H01L21/76835 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02131 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/022 ,  H01L21/3121 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76813

摘要： A double layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first organic dielectric layer is deposited overlying the insulating layer. A second inorganic dielectric layer is deposited overlying the first dielectric layer. In a first method, a via pattern is etched into the second dielectric layer. The via pattern is etched into the first dielectric layer using the patterned second dielectric layer as a mask. Thereafter, a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings. In a second method, a trench pattern is etched into the second dielectric layer. Thereafter, a via pattern is etched through the second inorganic dielectric layer and the first organic dielectric layer to complete dual damascene openings. In a third method, a via pattern is etched into the second dielectric layer. Then, simultaneously, the via pattern is etched into the first dielectric layer and a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings in the fabrication of an integrated circuit device.

摘要翻译： 描述了双层低介电常数材料双镶嵌金属化工艺。 金属线被覆盖在半导体衬底上的绝缘层所覆盖。 沉积在绝缘层上的第一有机电介质层。 第二无机介电层沉积在第一介电层上。 在第一种方法中，通孔图案被蚀刻到第二介电层中。 使用图案化的第二介电层作为掩模将通孔图案蚀刻到第一介电层中。 此后，将沟槽图案蚀刻到第二无机介电层中以完成双镶嵌开口。 在第二种方法中，沟槽图案被蚀刻到第二介电层中。 此后，通过第二无机介电层和第一有机介电层蚀刻通孔图案以完成双镶嵌开口。 在第三种方法中，通孔图案被蚀刻到第二介电层中。 然后，同时，通孔图案被蚀刻到第一介电层中，并且沟槽图案被蚀刻到第二无机介电层中，以在集成电路器件的制造中完成双镶嵌开口。

公开(公告)号：US06764914B2

公开(公告)日：2004-07-20

申请号：US10290130

申请日：2002-11-07

申请人： Alex See ,  Cher Liang Randall Cha ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

发明人： Alex See ,  Cher Liang Randall Cha ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683

摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

摘要翻译： 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US06486515B2

公开(公告)日：2002-11-26

申请号：US10131536

申请日：2002-04-24

申请人： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

发明人： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

IPC分类号： H01L2362

CPC分类号： H01L27/0251 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. The interlevel dielectric layer is covered with a mask that covers the first contact openings. Second contact openings are opened through the interlevel dielectric layer, shallow trench isolations, and the oxide layer to the N+ region and P+ region. The mask is removed. The first and second contact openings are filled with a conducting layer to complete formation of an ESD device.

摘要翻译： 描述了使用绝缘体上硅技术形成静电放电装置的方法。 在硅半导体衬底内形成N阱。 将P +区注入到N阱的一部分内，并且将N +区注入到不被N阱占据的半导体衬底的一部分内。 在半导体衬底上形成氧化物层并图案化以形成到半导体衬底的开口。 外延硅层生长在开口内并覆盖氧化物层。 在延伸到下面的氧化物层的外延硅层内形成浅沟槽隔离区。 在浅沟槽隔离区域之间的外延硅层中和栅极电极和相关的源极和漏极区域上形成栅电极。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 用覆盖第一接触开口的掩模覆盖层间电介质层。 第二接触开口通过层间介质层，浅沟槽隔离层和氧化物层开放到N +区域和P +区域。 去除面具。 第一和第二接触开口填充有导电层以完成ESD装置的形成。

公开(公告)号：US06399431B1

公开(公告)日：2002-06-04

申请号：US09531786

申请日：2000-03-21

申请人： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong

发明人： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong

IPC分类号： H01L2170

CPC分类号： H01L21/84 ,  H01L27/0266 ,  H01L27/1203 ,  H01L29/78603

摘要： A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. A silicon-on-insulator substrate is provided comprising a semiconductor substrate underlying an oxide layer underlying a silicon layer. The silicon layer and oxide layer are patterned to form a gate electrode wherein the semiconductor substrate is exposed. Ions are implanted into the exposed semiconductor substrate to form source and drain regions adjacent to the gate electrode. Spacers are formed on sidewalls of the gate electrode. An interlevel dielectric layer is deposited overlying the gate electrode. Openings are formed through the interlevel dielectric layer to the source and drain regions and filled with a conducting layer. The conducting layer is patterned to form conducting lines to complete formation of an electrostatic discharge device using SOI technology in the fabrication of integrated circuits.

摘要翻译： 描述了使用绝缘体上硅技术形成静电放电装置的方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下方的半导体衬底。 图案化硅层和氧化物层以形成其中暴露半导体衬底的栅电极。 将离子注入到暴露的半导体衬底中以形成与栅电极相邻的源区和漏区。 隔板形成在栅电极的侧壁上。 沉积在栅电极上的层间电介质层。 开口通过层间介电层形成到源区和漏区，并填充有导电层。 图案化导电层以形成导线，以在集成电路的制造中使用SOI技术完成静电放电装置的形成。

公开(公告)号：US06376379B1

公开(公告)日：2002-04-23

申请号：US09495344

申请日：2000-02-01

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

IPC分类号： H01L21302

CPC分类号： H01L21/31144 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76829

摘要： A method of patterning a hard mask, the comprising the following steps. A semiconductor structure is provided. A conductor film is formed over the semiconductor structure. An oxide layer is formed over the conductor film. A patterned metal oxide layer is formed over the conductor film. The oxide layer and the conductor film are etched, using the metal oxide layer as a hard mask, to form a patterned structure.

摘要翻译： 图案化硬掩模的方法，包括以下步骤。 提供半导体结构。 在半导体结构上形成导体膜。 在导体膜上形成氧化物层。 在导体膜上形成图案化的金属氧化物层。 使用金属氧化物层作为硬掩模来蚀刻氧化物层和导体膜，以形成图案化结构。

公开(公告)号：US06284609B1

公开(公告)日：2001-09-04

申请号：US09435437

申请日：1999-11-22

申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Puay Ing Ong ,  Sang Yee Loong

发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Puay Ing Ong ,  Sang Yee Loong

IPC分类号： H01L21336

CPC分类号： H01L29/66628 ,  H01L21/2257 ,  H01L21/28026 ,  H01L21/2807 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7834

摘要： A new method of fabricating a sub-quarter micron MOSFET device is achieved. A semiconductor substrate is provided. Isolation regions are formed in this substrate. An oxide layer is provided overlying both the substrate and the isolation regions. The oxide layer is patterned and etched exposing two regions of the substrate. A selective epitaxial growth (SEG) is performed with in situ doping covering the two exposed substrate regions formed during the previous step. The doped SEG regions will form the source and drain contact regions of the MOSFET. The oxide layer region between the two doped SEG regions is then patterned and etched away exposing the substrate. This is followed by a gate oxide formation and either a polysilicon or metal gate deposition. Planarization is then performed on the surface to facilitate interconnection later in the process and to form the final gate structure. Thermal energy provided from processing steps or from a rapid thermal anneal (RTA) allows the doping atoms in the SEG regions to diffuse into the substrate thereby forming the active source/drain regions. This method allows precise control of the doping profile in the active source/drain region. An interlevel dielectric is then deposited over the entire surface. Contact holes are then etched in the interlevel dielectric and metalization patterned to allow interconnection to the completed MOSFET device.

摘要翻译： 实现了制造二分之一微米MOSFET器件的新方法。 提供半导体衬底。 在该衬底中形成隔离区。 提供覆盖衬底和隔离区域的氧化物层。 图案化和蚀刻氧化层暴露衬底的两个区域。 通过原位掺杂来执行选择性外延生长（SEG），覆盖在前一步骤期间形成的两个暴露的衬底区域。 掺杂的SEG区域将形成MOSFET的源极和漏极接触区域。 然后将两个掺杂的SEG区域之间的氧化物层区域图案化并蚀刻掉，暴露衬底。 之后是栅极氧化物形成和多晶硅或金属栅极沉积。 然后在表面上执行平面化，以便在该过程中稍后进行互连并形成最终的栅极结构。 从加工步骤或快速热退火（RTA）提供的热能允许SEG区域中的掺杂原子扩散到衬底中，从而形成有源源极/漏极区域。 该方法允许精确控制有源源极/漏极区域中的掺杂分布。 然后在整个表面上沉积层间电介质。 然后在层间电介质中蚀刻接触孔，并图案化金属化，以允许与完成的MOSFET器件互连。

公开(公告)号：US06261917B1

公开(公告)日：2001-07-17

申请号：US09567420

申请日：2000-05-09

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683 ,  H01L28/75

摘要： A method for fabricating a metal-oxide-metal capacitor is described. A first insulating layer is provided overlying a semiconductor substrate. A barrier metal layer and a first metal layer are deposited over the insulating layer. A titanium layer is deposited overlying the first metal layer. The titanium layer is exposed to an oxidizing plasma while simultaneously a portion of the titanium layer where the metal-oxide-metal capacitor is to be formed is exposed to light whereby the portion of the titanium layer exposed to light reacts with the oxidizing plasma to form titanium oxide. Thereafter, the titanium layer is removed, leaving the titanium oxide layer where the metal-oxide-metal capacitor is to be formed. A second metal layer is deposited overlying the first metal layer and the titanium oxide layer. The second metal layer, titanium oxide layer, and first metal layer are patterned to form a metal-oxide-metal capacitor wherein the second metal layer forms an upper plate electrode, the titanium oxide layer forms a capacitor dielectric, and the first metal layer forms a bottom plate electrode of the MOM capacitor.

摘要翻译： 对金属氧化物 - 金属电容器的制造方法进行说明。 第一绝缘层设置在半导体衬底上。 在绝缘层上沉积阻挡金属层和第一金属层。 沉积钛层沉积在第一金属层上。 将钛层暴露于氧化等离子体，同时将要形成金属 - 氧化物 - 金属电容器的钛层的一部分暴露于光，由此暴露于光的钛层的部分与氧化等离子体反应形成 氧化钛。 然后，除去钛层，留下要形成金属 - 氧化物 - 金属电容器的氧化钛层。 沉积在第一金属层和氧化钛层上的第二金属层。 对第二金属层，氧化钛层和第一金属层进行构图以形成金属氧化物 - 金属电容器，其中第二金属层形成上板电极，氧化钛层形成电容器电介质，第一金属层形成 MOM电容器的底板电极。

公开(公告)号：US06177324B1

公开(公告)日：2001-01-23

申请号：US09428568

申请日：1999-10-28

申请人： Jun Song ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Lap Chan

发明人： Jun Song ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Lap Chan

IPC分类号： H01L21336

CPC分类号： H01L29/66621 ,  H01L27/0266 ,  H01L29/0649 ,  H01L29/7834

摘要： A new method is provided for the creation of an ESD protection device for deep submicron semiconductor technology. An STI trench is created and filled with oxide. The surface of the STI region is polished after which a gate structure is created over the STI region. A high energy ESD implant is performed that is self-aligned with the created gate structure after which the EDS device structure is completed by implanting the source and drain regions of the ESD device.

摘要翻译： 提供了一种用于创建深亚微米半导体技术的ESD保护器件的新方法。 产生STI沟槽并填充氧化物。 抛光STI区域的表面，之后在STI区域上形成栅极结构。 执行高能量ESD注入，其与所产生的栅极结构自对准，之后通过注入ESD器件的源极和漏极区域来完成EDS器件结构。

公开(公告)号：US08898597B2

公开(公告)日：2014-11-25

申请号：US13835339

申请日：2013-03-15

申请人： Qing Yang ,  Shyue Fong Quek ,  Gek Soon Chua ,  Yee Mei Foong ,  Dong Qing Zhang ,  Yun Tang

发明人： Qing Yang ,  Shyue Fong Quek ,  Gek Soon Chua ,  Yee Mei Foong ,  Dong Qing Zhang ,  Yun Tang

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/705

摘要： An approach for methodology, and an associated apparatus, enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and/or a highly skilled engineer is disclosed. Embodiments include: determining first and second features of an IC design; determining a thickness of a resist layer of the IC design based on an aerial image of the IC design; determining a threshold value according to the thickness; and comparing the threshold value to a separation distance between the first and second features.

摘要翻译： 公开了一种用于方法学和相关设备的方法，其使模拟过程能够检查设计的完整性并且预测所产生的电路的可制造性，其考虑到处理纬度而没有长的周转时间和/或高技能的工程师。 实施例包括：确定IC设计的第一和第二特征; 基于IC设计的空中图像确定IC设计的抗蚀剂层的厚度; 根据厚度确定阈值; 以及将阈值与第一和第二特征之间的间隔距离进行比较。