POLARIZATION CONTROL SYSTEM AND PROJECTOR
    21.
    发明申请
    POLARIZATION CONTROL SYSTEM AND PROJECTOR 有权
    极化控制系统和投影机

    公开(公告)号:US20090067049A1

    公开(公告)日:2009-03-12

    申请号:US12204239

    申请日:2008-09-04

    IPC分类号: G02B27/28 G02B27/10

    摘要: A phase compensation element is disposed between a reflective type display element and a polarizing beam splitter. Composed of a crystal structure retardation layer functioning as a quarter-wave plate and an inclined-axis retardation layer functioning as an O-plate, the phase compensation element is aligned substantially parallel to a reflective surface of the reflective type display element. The inclined-axis retardation layer is made of inorganic material obliquely deposited on the crystal structure retardation layer. The inclined-axis retardation layer has a principal refractive index axis inclined at between 0° and 45° to a surface normal of the crystal structure retardation layer, and has a thickness not to increase haze of the phase compensation element.

    摘要翻译: 相位补偿元件设置在反射型显示元件和偏振光束分离器之间。 由用作四分之一波片的晶体结构延迟层和用作O板的斜轴延迟层构成,相位补偿元件基本上平行于反射型显示元件的反射表面排列。 倾斜轴相位差层由倾斜地沉积在晶体结构相位差层上的无机材料制成。 倾斜轴延迟层的主折射率轴相对于晶体结构延迟层的表面法线倾斜0°至45°,并且具有不增加相位补偿元件的雾度的厚度。

    Optical communication system
    22.
    发明授权
    Optical communication system 有权
    光通信系统

    公开(公告)号:US07221846B2

    公开(公告)日:2007-05-22

    申请号:US11361962

    申请日:2006-02-27

    IPC分类号: G02B6/00

    CPC分类号: G02B6/02038 G02B6/4206

    摘要: In an optical communication system in which communication is conducted by transmitting light through a plastic optical fiber with a core diameter in the range from 300 to 600 μm, the average beam diameter and beam divergence angle expressed in terms of numerical aperture (NA) of the light at the input face of the optical fiber are set less than or equal to 250 μm, more preferably less than or equal to 200 μm, and less than or equal to 0.25, more preferably less than or equal to 0.2 respectively.

    摘要翻译: 在通过使光通过芯直径在300至600μm的塑料光纤进行通信的光通信系统中,平均光束直径和光束发散角以表示的数值孔径(NA)表示 在光纤的输入面上的光被设定为小于或等于250μm,更优选小于等于200μm,小于等于0.25,更优选小于或等于0.2。

    Light emitting apparatus
    23.
    发明申请
    Light emitting apparatus 有权
    发光装置

    公开(公告)号:US20070096114A1

    公开(公告)日:2007-05-03

    申请号:US11527387

    申请日:2006-09-27

    摘要: A light emitting apparatus which has a high output power and does not experience a decrease in the emission output power is provided. The light emitting apparatus comprises a light emitting element which has one of main surfaces thereof being used as a light emitting surface and a plurality of side faces having different areas, and a support member which has a recess with metallic members provided on the side wall surfaces thereof for reflecting the light emitted by the light emitting element. The light emitting element is placed in the recess so that the distance between the metallic member and a side face having the largest surface area among the plurality of side faces of the light emitting element is larger than the distance between the metallic member and the other side face.

    摘要翻译: 提供了具有高输出功率并且没有经历发射输出功率的降低的发光装置。 发光装置包括:发光元件,其主表面中的一个被用作发光表面和具有不同面积的多个侧面;以及支撑构件,其具有设置在侧壁表面上的金属构件的凹部 用于反射由发光元件发出的光。 发光元件放置在凹部中,使得金属构件与发光元件的多个侧面中具有最大表面积的侧面之间的距离大于金属构件与另一侧之间的距离 面对。

    Micro controller unit
    24.
    发明授权
    Micro controller unit 有权
    微控制器单元

    公开(公告)号:US07167996B2

    公开(公告)日:2007-01-23

    申请号:US10690574

    申请日:2003-10-23

    IPC分类号: G06F1/12

    摘要: It is an object to increase a speed of a CPU operation irrespective of an operation speed of a peripheral circuit and to prevent an increase in power consumption from being thereby caused. A clock generating circuit (10) generates two clocks having phases which are equal to each other, that is, a CPU clock (CLKCPU) and a bus clock (CLKBUS). A BIU (bus interface unit) (51) controls a code bus based on the CPU clock (CLKCPU) and controls a peripheral bus based on the bus clock (CLKBUS). The clock generating circuit (10) switches a frequency of each of the CPU clock (CLKCPU) and the bus clock (CLKBUS) depending on an operation mode of an MCU. For example, a speed of the CPU clock (CLKCPU) is set to be higher than that of the bus clock (CLKBUS) in order to carry out a high-speed operation of a CPU. Also in that case, the phases of both clocks are equal to each other. Consequently, the code bus and the peripheral bus in the BIU (51) can easily be controlled.

    摘要翻译: 本发明的目的是提高CPU运行的速度,而与外围电路的运行速度无关,并且防止由此引起的功耗的增加。 时钟发生电路(10)产生具有彼此相等的相位的两个时钟,即CPU时钟(CLK< CPU>)和总线时钟(CLK< BUS< )。 BIU(总线接口单元)(51)基于CPU时钟(CLK )来控制代码总线,并且基于总线时钟(CLK )。 时钟发生电路(10)根据MCU的工作模式切换CPU时钟(CLK CPU )和总线时钟(CLK 。 例如,CPU时钟的速度(CLK< CPU<>)被设定为高于总线时钟(CLK< BUS>)的速度, CPU的高速运行。 同样在这种情况下,两个时钟的相位彼此相等。 因此,可以容易地控制BIU(51)中的代码总线和外围总线。

    Semiconductor device with clock signal selection circuit
    27.
    发明授权
    Semiconductor device with clock signal selection circuit 有权
    具有时钟信号选择电路的半导体器件

    公开(公告)号:US06550043B1

    公开(公告)日:2003-04-15

    申请号:US09511709

    申请日:2000-02-23

    申请人: Hiroki Takahashi

    发明人: Hiroki Takahashi

    IPC分类号: G06F1750

    CPC分类号: G06F1/08

    摘要: In accordance with a recent high-speed trend of the CPU, it has been demanded a semiconductor device which is capable of varying the frequency of a clock signal to be input to the CPU in accordance with the access speed of the individual peripheral devices, but without using a wait controller so as to readily cope with the case where a low-speed access peripheral device is to be accessed, and in order to meet with this demand, the semiconductor device of the present invention comprises a CPU, an address decoder that decodes an address signal transmitted from the CPU and outputs an address signal specifying signal for specifying an address area in which a designated address is included, a frequency divider that divides a base clock signal and outputs one or more than one low-speed clock signals whose frequencies have been lowered, and a clock signal decision circuit that selects as to which one of the base clock signal and the frequency-divided clock signals is to be input to the CPU in accordance with the address area specifying signal output from said address decoder.

    摘要翻译: 根据CPU的近期高速趋势,已经要求能够根据各个外围设备的访问速度来改变要输入到CPU的时钟信号的频率的半导体器件,但是 而不使用等待控制器,以便容易地应对要访问低速存取周边设备的情况,并且为了满足这种需求,本发明的半导体器件包括CPU,地址解码器 解码从CPU发送的地址信号,并输出用于指定包括指定地址的地址区域的地址信号指定信号,分频器,其分频基本时钟信号并输出​​一个或多于一个低速时钟信号, 频率降低,并且选择基准时钟信号和分频时钟信号中哪一个要输入到CPU的时钟信号判定电路 根据从所述地址解码器输出的地址区域指定信号。

    Semiconductor memory device having a plurality of banks activated by a
common timing control circuit
    28.
    发明授权
    Semiconductor memory device having a plurality of banks activated by a common timing control circuit 有权
    具有由公共定时控制电路激活的多个存储体的半导体存储器件

    公开(公告)号:US6088292A

    公开(公告)日:2000-07-11

    申请号:US199052

    申请日:1998-11-24

    申请人: Hiroki Takahashi

    发明人: Hiroki Takahashi

    CPC分类号: G11C7/22 G11C11/4094 G11C8/18

    摘要: A semiconductor memory includes a plurality of banks, a timing control circuits, and latch circuits. The timing control circuit is arranged commonly to the plurality of banks and outputs a signal for activating each bank and a signal for precharging each bank in a predetermined order at predetermined timings. Each latch circuit is arranged for each bank and latches the state of a signal output from the timing control circuit.

    摘要翻译: 半导体存储器包括多个存储体,定时控制电路和锁存电路。 定时控制电路被共同地布置到多个存储体,并且以预定的顺序输出用于激活每个存储体的信号和用于以预定顺序对每个存储体预充电的信号。 每个锁存电路被布置用于每个存储体并锁存从定时控制电路输出的信号的状态。

    Lever-coupling type connector
    29.
    发明授权
    Lever-coupling type connector 失效
    杠杆连接型连接器

    公开(公告)号:US5676556A

    公开(公告)日:1997-10-14

    申请号:US531656

    申请日:1995-09-21

    IPC分类号: H01R13/629 H01R3/00

    CPC分类号: H01R13/62933

    摘要: A lever-coupling type connector includes a pair of one and other connector housings to be fit into each other; a lever rotatably supported by the one connector housing and having a guiding groove; the other connector housing having an introducing protrusion to be engaged with the guiding groove; wherein the lever has a locking hook protruded from its supporting shaft, and the one connector housing includes an elastic locking piece having an elastic step to be engaged with the locking hook when the lever is rotated in a direction of coupling both connector housings. The lever is urged in an anti-fitting direction by the elastic force of the elastic locking piece in a state where both connector housings are completed fit into each other. This permits the state of semi-fitting of both connector housings to be easily recognized.

    摘要翻译: 杠杆连接型连接器包括彼此配合的一对一个和另一个连接器壳体; 由所述一个连接器壳体可旋转地支撑并具有引导槽的杆; 所述另一连接器壳体具有与所述引导槽接合的引入突起; 其中所述杠杆具有从其支撑轴突出的锁定钩,并且所述一个连接器壳体包括弹性锁定片,所述弹性锁定片具有弹性踏板,当所述杠杆沿联接两个连接器壳体的方向旋转时,所述弹性锁定件与所述锁定钩接合。 在两个连接器壳体完全相互配合的状态下,通过弹性锁定件的弹性力使杠杆以防装配方向被推动。 这允许容易地识别两个连接器壳体的半嵌入状态。

    Lever fitting-type connector
    30.
    发明授权
    Lever fitting-type connector 失效
    杠杆接头型连接器

    公开(公告)号:US5484297A

    公开(公告)日:1996-01-16

    申请号:US312798

    申请日:1994-09-27

    IPC分类号: H01R13/629 H01R13/62

    CPC分类号: H01R13/62933

    摘要: A lever fitting-type connector includes a lever returning spring having a connector-side engagement lever and a lever-side engagement lever which extend from a coil portion, a connector housing including a shaft portion and one spring end engagement portion which are formed on an outer wall surface thereof, and the one spring end engagement portion engaged with the connector-side engagement lever; and a U-shaped lever having an engagement hole for the shaft portion and the other spring end engagement portion which is engaged with the lever side coil portion.

    摘要翻译: 杠杆装配型连接器包括具有连接器侧接合杆的杆复位弹簧和从线圈部延伸的杠杆侧接合杆,连接器壳体包括轴部和一个弹簧端接合部, 一个弹簧端接合部分与连接器侧接合杆接合; 以及具有用于轴部的接合孔和与杠杆侧线圈部接合的另一弹簧端接合部的U形杆。