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公开(公告)号：US06967380B2
公开(公告)日：2005-11-22
申请号：US10722867
申请日：2003-11-26
IPC分类号： H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823878 , H01L21/823892
摘要： A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.
摘要翻译： 形成逆行n井和p井的方法。 在基板上形成第一掩模，并执行n阱注入。 然后将掩模变薄，并用较薄的n面罩进行深度p植入。 这防止了在n阱中形成的在n阱中形成的FET的Vt偏移。 然后去除变薄的掩模，将p-阱掩模放置就位，并且执行其余的p阱注入。
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22.发明授权公开(公告)号：US06649429B2
公开(公告)日：2003-11-18
申请号：US10194642
申请日：2002-07-11
IPC分类号： H01L2166
CPC分类号： H01L23/544 , G01N2203/0016 , G01N2203/0025 , G01N2203/0286 , G01N2203/0617 , H01L21/67288 , H01L22/12 , H01L22/34 , H01L29/7842 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method is presented for measuring and monitoring the mechanical stress at the device level which occurs intrinsically during the fabrication process or which is induced via extrinsic means. The method applies the fact that the current-voltage (I-V) characteristics of a diode change as the diode is subjected to mechanical stress. The method is applicable to monitoring stress at the microscopic and device levels at various stages in the semiconductor wafer fabrication process. Apparatus for implementing the method is also presented.
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公开(公告)号：US06417070B1
公开(公告)日：2002-07-09
申请号：US09735988
申请日：2000-12-13
申请人： Arne W. Ballantine , Jeffrey S. Brown , Jeffrey D. Gilbert , James J. Quinlivan , James A. Slinkman , Anthony C. Speranza
发明人： Arne W. Ballantine , Jeffrey S. Brown , Jeffrey D. Gilbert , James J. Quinlivan , James A. Slinkman , Anthony C. Speranza
IPC分类号： H01L2176
CPC分类号： H01L21/76235 , H01L21/31662
摘要： A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.
摘要翻译： 通过快速热氧化获得包括具有在沟槽的顶部和底部具有圆角的衬垫的沟槽的结构。
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公开(公告)号：US5065103A
公开(公告)日：1991-11-12
申请号：US499857
申请日：1990-03-27
摘要： An apparatus and method for generating microscopic scan data of C-V and/or dC/dV over a scan area. A scanning microscope, for example a scanning force microscope, is provided with a voltage biased tip, for example, of tungsten, which is scanned across an area to derive the data. The data can be used to derive a plot of semiconductor dopant level across the scan area. Other material properties can be derived, for example, carrier generation and recombination rates and subsurface defects.
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25.发明授权SOI radio frequency switch with enhanced signal fidelity and electrical isolation 有权具有增强的信号保真度和电隔离的SOI射频开关公开(公告)号：US08916467B2
公开(公告)日：2014-12-23
申请号：US13116396
申请日：2011-05-26
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H03K3/01 , H01L21/336 , G06F17/50 , H01L21/762 , H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76224 , H01L21/76251 , H01L21/84
摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.
摘要翻译： 具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。 至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。 掺杂接触区域被偏置在处于或接近RF开关中的峰值电压的电压，该电压去除感应电荷层内的少数电荷载流子。 少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。 诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。 还提供了用于半导体结构的设计结构。
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26.发明授权Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer 有权具有降低电荷层的绝缘体上硅高带宽电路的方法，设备和设计结构公开(公告)号：US08492868B2
公开(公告)日：2013-07-23
申请号：US12848558
申请日：2010-08-02
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76283 , H01L21/84 , H01L27/0211 , H01L27/0617 , H01L27/1203
摘要： A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.
摘要翻译： 一种方法，集成电路和设计结构包括具有沟槽结构的硅衬底层和离子杂质植入物。 绝缘体层位于硅衬底层上并接触硅衬底层。 绝缘体层填充沟槽结构。 电路层位于掩埋绝缘体层上并与其接触。 电路层包括由被动结构分开的一组有源电路。 当从顶视图观察集成电路结构时，沟槽结构位于有源电路组之间。 因此，当从顶视图观察集成电路结构时，沟槽结构在被动结构之下并且不在电路组下方。
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27.发明授权公开(公告)号：US08492294B2
公开(公告)日：2013-07-23
申请号：US13608314
申请日：2012-09-10
申请人： Joseph R. Greco , Kevin Munger , Richard A. Phelps , Jennifer C. Robbins , William Savaria , James A. Slinkman , Randy L. Wolf
发明人： Joseph R. Greco , Kevin Munger , Richard A. Phelps , Jennifer C. Robbins , William Savaria , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L21/00
CPC分类号： H01L21/7624 , H01L21/26506 , H01L21/84 , H01L27/1203
摘要： A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.
摘要翻译： 绝缘体上半导体衬底和相关半导体结构以及绝缘体上半导体衬底和相关半导体结构的制造方法提供了一种位于并形成在基底半导体内的多阶射频谐波抑制区域 在绝缘体上半导体衬底内的掩埋介质层与基底半导体衬底的界面下方的位置处的衬底。 多级射频谐波抑制区域可以包括离子注入原子，例如但不限于稀有气体原子，以在对射频设备供电时提供抑制的多阶射频谐波，例如但不限于无线电 位于和形成在半导体结构内的表面半导体层内和之上的高频互补金属氧化物半导体器件（或替代地，无源器件）。
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28.发明申请LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED DIELECTRIC PLATES TO ACHIEVE A HIGH DRAIN-TO-BODY BREAKDOWN VOLTAGE, A METHOD OF FORMING THE TRANSISTOR AND A PROGRAM STORAGE DEVICE FOR DESIGNING THE TRANSISTOR 有权具有切割介质板的横向延伸的漏极金属氧化物半导体场效应晶体管（LEDMOSFET），以实现高的漏极 - 体积断开电压，形成晶体管的方法和用于设计晶体管的程序存储器件公开(公告)号：US20120168766A1
公开(公告)日：2012-07-05
申请号：US12983439
申请日：2011-01-03
申请人： Michel J. Abou-Khalil , Alan B. Botula , Alvin J. Joseph , Theodore J. Letavic , James A. Slinkman
发明人： Michel J. Abou-Khalil , Alan B. Botula , Alvin J. Joseph , Theodore J. Letavic , James A. Slinkman
CPC分类号： H01L29/7824 , G06F17/5063 , H01L29/402 , H01L29/407 , H01L29/4238 , H01L29/66681 , H01L29/66704 , H01L29/66795 , H01L29/7825 , H01L29/785
摘要： A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb.
摘要翻译： 具有高漏极对体击穿电压（Vb）的横向延伸漏极，金属氧化物半导体场效应晶体管（LEDMOSFET）在漏极漂移区域的相对侧上并入门结构延伸。 延伸部是锥形的，使得每个延伸部和漂移区域之间的距离从邻近通道区域的一端线性地增加到与漏极区域相邻的另一端部。 在一个实施例中，这些扩展可以垂直延伸通过围绕LEDMOSFET的隔离区域。 在另一个实施例中，扩展可以位于隔离区域的顶部。 在任一种情况下，扩展在漏极漂移内产生强大的基本均匀的水平电场分布。 还公开了通过限定扩展的尺寸来形成具有特定Vb的LEDMOSFET的方法以及用于将LEDMOSFET设计为具有特定Vb的程序存储装置。
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公开(公告)号：US08133774B2
公开(公告)日：2012-03-13
申请号：US12411494
申请日：2009-03-26
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/76264 , H01L27/1203
摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.
摘要翻译： 至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。 浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。 所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。 感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。
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30.发明申请METHOD, APPARATUS, AND DESIGN STRUCTURE FOR SILICON-ON-INSULATOR HIGH-BANDWIDTH CIRCUITRY WITH REDUCED CHARGE LAYER 有权具有减少充电层的绝缘体绝缘子高带宽电路的方法，装置和设计结构公开(公告)号：US20120025345A1
公开(公告)日：2012-02-02
申请号：US12848558
申请日：2010-08-02
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76283 , H01L21/84 , H01L27/0211 , H01L27/0617 , H01L27/1203
摘要： A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.
摘要翻译： 一种方法，集成电路和设计结构包括具有沟槽结构的硅衬底层和离子杂质植入物。 绝缘体层位于硅衬底层上并接触硅衬底层。 绝缘体层填充沟槽结构。 电路层位于掩埋绝缘体层上并与其接触。 电路层包括由被动结构分开的一组有源电路。 当从顶视图观察集成电路结构时，沟槽结构位于有源电路组之间。 因此，当从顶视图观察集成电路结构时，沟槽结构在被动结构之下并且不在电路组下方。
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