公开(公告)号：US20060098523A1

公开(公告)日：2006-05-11

申请号：US11313963

申请日：2005-12-22

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C8/00

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

公开(公告)号：US20060030517A1

公开(公告)日：2006-02-09

申请号：US11019360

申请日：2004-12-23

申请人： Toshikazu Nakamura

发明人： Toshikazu Nakamura

IPC分类号： A61K38/18

CPC分类号： A61K38/1833

摘要： The invention relates to an anti-cancer agent containing α-chain protein (α-fragment) of HGF (hepatocyte growth factor) as an active ingredient. The active ingredient of α-fragment has a specific suppressing effect on invasion and metastasis of cancer cells such as gallbladder cancer, lung cancer and other, which are highly metastatic and result in a high mortality. Therefore, the agent of the invention is used in treatment and prevention of cancer as an anti-cancer agent, and is extremely useful clinically.

公开(公告)号：US20050221441A1

公开(公告)日：2005-10-06

申请号：US11041363

申请日：2005-01-25

申请人： Toshikazu Nakamura ,  Kunio Matsumoto ,  Kazuhiro Fukuta

发明人： Toshikazu Nakamura ,  Kunio Matsumoto ,  Kazuhiro Fukuta

IPC分类号： A61K38/00 ,  C07K14/475 ,  C07H21/04 ,  C12N15/09

CPC分类号： C07K14/4753

摘要： The present invention provides a segment of glycosylation-deficient HGF having mutation(s) introduced into an amino acid sequence so as to prevent glycosylation at least one glycosylation site of a hepatocyte growth factor (HGF), and a method of producing the same. The segment of glycosylation-deficient HGF of the present invention has the same activity as that of a segment of glycosylated HGF, therefore, it is useful as an alternate for a segment of glycosylated HGF.

摘要翻译： 本发明提供具有引入氨基酸序列的突变的糖基化缺陷型HGF片段，以防止肝细胞生长因子（HGF）的至少一个糖基化位点的糖基化及其制备方法。 本发明的糖基化缺陷型HGF片段具有与糖基化HGF片段相同的活性，因此，作为糖基化HGF片段的替代物是有用的。

公开(公告)号：US06925027B2

公开(公告)日：2005-08-02

申请号：US10698450

申请日：2003-11-03

申请人： Satoshi Eto ,  Toshikazu Nakamura ,  Toshiya Miyo

发明人： Satoshi Eto ,  Toshikazu Nakamura ,  Toshiya Miyo

IPC分类号： G11C11/403 ,  G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4193 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067

摘要： A semiconductor memory with a memory core for dynamically holding data in which a data collision at the time of the semiconductor memory making the transition from a standby state to a nonstandby state is prevented. A first buffer circuit inputs an enable signal for controlling a standby state or a nonstandby state. A second buffer circuit outputs a predetermined logic signal or a read/write signal for controlling the reading of data from or the writing of data to the memory core in accordance with the enable signal. A third buffer circuit outputs an inverted signal obtained by inverting the logic signal or the read/write signal in accordance with the enable signal. A control circuit controls the reading or writing of the data by the read/write signal outputted from the second buffer circuit. A data output control circuit controls the inputting of the data from or the outputting of the data to the outside by the inverted signal or the read/write signal outputted from the third buffer circuit.

摘要翻译： 一种具有用于动态保持数据的存储器的半导体存储器，其中半导体存储器从待机状态转换到非状态时的数据冲突被防止。 第一缓冲电路输入用于控制待机状态或非状态的使能信号。 第二缓冲电路根据使能信号输出预定的逻辑信号或读/写信号，用于控制数据的读取或向数据的写入。 第三缓冲电路根据使能信号输出通过反相逻辑信号或读/写信号而获得的反相信号。 控制电路通过从第二缓冲电路输出的读/写信号来控制数据的读取或写入。 数据输出控制电路通过从第三缓冲电路输出的反相信号或读/写信号来控制数据的输入或输出到外部。

公开(公告)号：US20050159835A1

公开(公告)日：2005-07-21

申请号：US11021112

申请日：2004-12-23

申请人： Kentaro Yamada ,  Yukihiro Aoyama ,  Makoto Ogawa ,  Toshikazu Nakamura ,  Yoshikazu Aikawa

发明人： Kentaro Yamada ,  Yukihiro Aoyama ,  Makoto Ogawa ,  Toshikazu Nakamura ,  Yoshikazu Aikawa

IPC分类号： G05B19/418 ,  C23C14/34 ,  G05B23/02 ,  G06F17/30 ,  G06F19/00 ,  G06G7/48 ,  G06Q50/00 ,  G06Q50/04 ,  H01L21/00 ,  H01L21/02 ,  H01L21/66 ,  H04L9/00

CPC分类号： G06Q10/06

摘要： A model creating device inputs process status data that are obtained in time series during a period during which each of process steps of a process is carried out and are related to status of this process, as well as inspection result data related to object articles that were processed by said process. An extracting part extracts a characteristic quantity from the process status data for every unit object article and for every process step. An analyzing part carries out an analysis by data mining by using the characteristic quantities and inspection result data in correlation with the unit object articles and creates a process-quality model that shows a relationship between the correlated characteristic quantities and inspection result data.

摘要翻译： 模型创建装置输入在过程的每个处理步骤被执行并且与该过程的状态相关的时段期间以时间序列获得的过程状态数据以及与对象物品相关的检查结果数据 由所述过程处理。 提取部分从每个单位物品的处理状态数据和每个处理步骤中提取特征量。 分析部分通过使用与单位对象物品相关的特征量和检查结果数据进行数据挖掘分析，并创建显示相关特征量与检验结果数据之间的关系的过程质量模型。

公开(公告)号：US20050052941A1

公开(公告)日：2005-03-10

申请号：US10965951

申请日：2004-10-18

申请人： Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo

发明人： Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo

IPC分类号： G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C8/02

CPC分类号： G11C11/40603 ,  G11C7/22 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2281 ,  G11C2211/4061

摘要： A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.

摘要翻译： 定时器从接收外部接入信号测量预定时间，并且在经过预定时间之后输出接入请求信号。 外部访问信号使存储器核心执行读取操作，并且访问请求信号使得存储器核心操作。 预定时间被设定为比存储器芯执行单次操作的核心操作时间长。 因此，当外部访问信号在比预定时间短的时间内变化时，存储器核不执行操作。 因此，即使当存储器核心不能正常操作的间隔提供外部访问信号时，也可以防止存储器芯故障并保留其中的数据崩溃。

公开(公告)号：US06855685B2

公开(公告)日：2005-02-15

申请号：US09951629

申请日：2001-09-14

申请人： Toshikazu Nakamura

发明人： Toshikazu Nakamura

IPC分类号： A61K38/18 ,  A01N37/18 ,  A61K38/00 ,  A61K39/00 ,  C07K17/00

CPC分类号： A61K38/1833

摘要： The invention relates to an anti-cancer agent containing α-chain protein (α-fragment) of HGF (hepatocyte growth factor) as an active ingredient. The active ingredient of α-fragment has a specific suppressing effect on invasion and metastasis of cancer cells such as gallbladder cancer, lung cancer and other, which are highly metastatic and result in a high mortality. Therefore, the agent of the invention is used in treatment and prevention of cancer as an anti-cancer agent, and is extremely useful clinically.

摘要翻译： 本发明涉及含有作为活性成分的HGF（肝细胞生长因子）的α-链蛋白（α-片段）的抗癌剂。 α-片段的活性成分对癌细胞如胆囊癌，肺癌等侵袭转移具有特异性的抑制作用，其具有高度的转移性，导致高死亡率。 因此，本发明的药剂用于治疗和预防癌症作为抗癌剂，临床非常有用。

公开(公告)号：US06512717B2

公开(公告)日：2003-01-28

申请号：US08690652

申请日：1996-07-29

申请人： Satoshi Eto ,  Masato Matsumiya ,  Shusaku Yamaguchi ,  Toshikazu Nakamura ,  Hideki Kano ,  Ayako Kitamoto ,  Mitsuhiro Higashiho

发明人： Satoshi Eto ,  Masato Matsumiya ,  Shusaku Yamaguchi ,  Toshikazu Nakamura ,  Hideki Kano ,  Ayako Kitamoto ,  Mitsuhiro Higashiho

IPC分类号： G11C800

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C11/4097

摘要： A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.

摘要翻译： 半导体存储器件包括由存储块形成的核心区域，每个存储器块具有放松的读出放大器布置，数据总线包括与存储块对应的数据总线;多个输入/输出端子，其数量对应于数据总线形成 数据总线以及在数据总线之间设置的输入/输出端子之间的数据通路开关电路，用于提供输入/输出端子与数据总线之间的互连路径，其中数据路径切换电路将部分互连路径切换到 响应于开关控制信号，使得输入/输出端子分别连接到位于任何存储器块中相应的预定物理位置处的预定存储器单元。

公开(公告)号：US06368534B1

公开(公告)日：2002-04-09

申请号：US09612245

申请日：2000-07-07

申请人： Toshikazu Nakamura ,  Yukihiro Katai

发明人： Toshikazu Nakamura ,  Yukihiro Katai

IPC分类号： C08J518

CPC分类号： C08J5/18 ,  B29C41/28 ,  B29D7/01 ,  B29K2001/00 ,  C08J2301/12

摘要： This invention relates to a solution casting process capable of decreasing uneven coating of a functional layer upon applying the functional layer onto a film surface, which comprises casting a solution of polymer dissolved in organic solvent into a film by extruding from a die onto a support, wherein the length of the film from the die opening to the landing of the film on the support is controlled to 3 to 40 mm.

摘要翻译： 本发明涉及一种在将功能层施加到膜表面上时能够减少功能层不均匀涂覆的溶液流延法，其包括将溶解在有机溶剂中的聚合物溶液通过从模具挤出到载体上而成膜， 其中将膜从模具开口到支撑体上的膜的着陆的长度被控制为3至40mm。

公开(公告)号：US6147919A

公开(公告)日：2000-11-14

申请号：US274245

申请日：1999-03-23

申请人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

发明人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

IPC分类号： H01L27/10 ,  G11C7/06 ,  G11C7/12 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C7/12

摘要： A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks. The local drivers apply a selection signal to the second selection lines according to a selection signal from the first selection lines. The write-only column selection lines are controlled by signals that are used to control the sense amplifiers.

摘要翻译： 半导体存储器具有排列成阵列的存储单元，布置在每个存储单元列中的直接型读出放大器，用于向要被访问的存储单元写入数据和从存储单元读取数据;列选择线，用于选择读取放大器 涉及要访问的存储器单元的列，只读列选择线，用于选择存储单元被访问以涉及要访问的存储器单元的行的读出放大器以写入数据，以及本地驱动器。 读出放大器在每行中分组成读出放大器模块。 只写列选择线由用于选择读入放大器块的第一选择线组成，所述读出放大器块包括要被存取的存储单元以进行数据写入，第二选择线用于选择包含在所选择的读出放大器块中的读出放大器 。 本地驱动器根据来自第一选择线的选择信号向第二选择线施加选择信号。 只写列选择线由用于控制读出放大器的信号控制。