公开(公告)号：US09073866B2

公开(公告)日：2015-07-07

申请号：US13761306

申请日：2013-02-07

申请人： Shinzo Kagabu ,  Masaaki Mitomi ,  Shigeki Kitsuda ,  Ryo Horikoshi ,  Masahiro Nomura ,  Yasumichi Onozaki

发明人： Shinzo Kagabu ,  Masaaki Mitomi ,  Shigeki Kitsuda ,  Ryo Horikoshi ,  Masahiro Nomura ,  Yasumichi Onozaki

IPC分类号： A01N47/40 ,  C07D213/36 ,  C07D213/61 ,  C07D211/98 ,  A01N43/40 ,  A01N43/50 ,  A01N43/78 ,  C07C233/05 ,  C07C233/12 ,  C07C261/04 ,  C07C271/12 ,  C07C311/09 ,  C07F9/58 ,  C07D401/06

CPC分类号： A01N43/40 ,  A01N37/18 ,  A01N43/50 ,  A01N43/54 ,  A01N43/58 ,  A01N43/78 ,  A01N47/02 ,  A01N47/12 ,  A01N47/40 ,  A01N57/32 ,  C07C233/05 ,  C07C233/12 ,  C07C261/04 ,  C07C271/12 ,  C07C311/09 ,  C07D211/98 ,  C07D213/36 ,  C07D213/40 ,  C07D213/42 ,  C07D213/61 ,  C07D213/75 ,  C07D237/08 ,  C07D277/32 ,  C07D333/20 ,  C07D401/06 ,  C07D401/12 ,  C07D405/12 ,  C07D417/12 ,  C07F9/58

摘要： Specific amine derivatives have been found to possess excellent activities as pest control agents.

摘要翻译： 已发现特定的胺衍生物作为害虫控制剂具有优良的活性。

公开(公告)号：US08996940B2

公开(公告)日：2015-03-31

申请号：US13349279

申请日：2012-01-12

申请人： Masahiro Nomura ,  Taro Sakurabayashi

发明人： Masahiro Nomura ,  Taro Sakurabayashi

IPC分类号： G01R31/28 ,  H03K3/037 ,  G01R31/3185 ,  H03K19/00

CPC分类号： H03K19/1731 ,  G01R31/318575 ,  H03K3/0375 ,  H03K19/0008 ,  H03K19/0016 ,  H03K19/17728 ,  H03K19/1776

摘要： A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops.

摘要翻译： 半导体集成电路具有：N个输入端子; N个输出端子; 多个触发器，包括N个触发器和R个冗余触发器; 选择器部分，被配置为根据重新配置信息从多个触发器中选择N个选择的触发器，并且切换数据流，使得输入到N个输入端的数据通过N个选择的触发器分别输出到N个输出端， 翻牌 和错误检测部。 在测试模式下，N个触发器形成扫描链，扫描数据被输入到扫描链。 误差检测部分在测试模式下，基于在N个触发器中分别输入/输出的扫描输入/输出数据来检测包括在N个触发器中的错误触发器，并进一步产生重新配置信息， N选择的触发器不包括错误触发器。

公开(公告)号：US08795442B2

公开(公告)日：2014-08-05

申请号：US12162878

申请日：2007-03-29

申请人： Yoichi Mukai ,  Shinji Kozuma ,  Masahiro Nomura

发明人： Yoichi Mukai ,  Shinji Kozuma ,  Masahiro Nomura

IPC分类号： C22C38/00 ,  B32B3/00

CPC分类号： C21D9/46 ,  C22C38/02 ,  C22C38/04 ,  C22C38/06 ,  Y10T428/12993

摘要： The invention provides a high strength cold rolled steel sheet having excellent chemical conversion treatment property stably even Mo is added aiming high strengthening. The surface property of the cold rolled steel sheet satisfies that the characteristic of 10 μm or more of the maximum depth (Ry) of the unevenness and 30 μm or less of the average spacing (Sm) of the unevenness, and that either one or more preferably both of, the characteristic of the load length ratio (tp40) of the unevenness of the surface is 20% or less, and the characteristic of the difference of the load length ratios (tp60) and (tp40) is 60% or more, is satisfied, and the crack of 3 μm or less width and 5 μm or more depth does not exist on the surface.

摘要翻译： 本发明提供了一种具有优异的化学转化处理性能的高强度冷轧钢板，即使添加Mo以达到高强度。 冷轧钢板的表面性能满足不平坦部的最大深度（Ry）为10μm以上，凹凸的平均间隔（Sm）为30μm以下的特性， 优选地，表面的不平坦度的负载长度比（tp40）的特性都为20％以下，负载长度比（tp60）和（tp40）的差的特性为60％以上， 并且表面上不存在3μm以下的宽度和5μm以上的深度的裂纹。

公开(公告)号：US20130070402A1

公开(公告)日：2013-03-21

申请号：US13699441

申请日：2011-06-22

申请人： Masatoshi Shimizu ,  Masahiro Nomura

发明人： Masatoshi Shimizu ,  Masahiro Nomura

IPC分类号： H05K5/02 ,  B24C1/10

CPC分类号： H05K5/0243 ,  B24C1/10 ,  C23C24/106 ,  H05K5/02 ,  H05K5/04

摘要： An enclosure that contains a transmission section and a reception section of an ODU is protected against hard environments without it being necessary to apply a coating of paint to the enclosure. The present invention is communication device (ODU) (1) installed outdoors, including a transmission section that transmits a signal; a reception section that receives a signal;and an enclosure that contains the transmission section and the reception section. In the device, the enclosure of ODU (1) is made of a nonferrous metal and an outer surface of the nonferrous metal is coated with paint, but a concave and convex pattern of an impact mark of powder particles is successively formed thereon.

摘要翻译： 包含ODU的传输部分和接收部分的机箱可防止恶劣环境，而无需将油漆涂覆在外壳上。 本发明是安装在户外的通信设备（ODU）（1），包括发送信号的发送部分; 接收部分，其接收信号; 以及包含发送部和接收部的外壳。 在该装置中，ODU（1）的外壳由有色金属制成，有色金属的外表面涂上涂料，但在其上依次形成有粉末颗粒的冲击痕迹的凹凸图案。

公开(公告)号：US20120218016A1

公开(公告)日：2012-08-30

申请号：US13462652

申请日：2012-05-02

申请人： Masahiro Nomura

发明人： Masahiro Nomura

IPC分类号： H03L7/00

CPC分类号： H03K5/135 ,  H03K5/26

摘要： A semiconductor integrated circuit device, includes a plurality of delay paths which are connected in parallel between synchronous operation circuits operating in synchronism with a clock signal and which enable transmission of a signal, a delay detection unit that detects respective delay times in the plurality of delay paths, and a control unit that selects one delay path from the plurality of delay paths based on a detection result of the delay detection unit, and controls blocking of signal transmission in the delay paths other than the selected one delay path. The control unit selects, as one delay path, a delay path whose delay time is a middle value among the plurality of delay paths.

摘要翻译： 一种半导体集成电路器件，包括在与时钟信号同步操作的同步操作电路中并联连接并且能够传输信号的多个延迟路径，延迟检测单元，其检测多个延迟中的各个延迟时间 路径和控制单元，其基于延迟检测单元的检测结果从多个延迟路径中选择一个延迟路径，并且控制除了所选择的一个延迟路径之外的延迟路径中的信号传输的阻塞。 作为一个延迟路径，控制部选择多个延迟路径中的延迟时间为中间值的延迟路径。

公开(公告)号：US08004351B2

公开(公告)日：2011-08-23

申请号：US12521605

申请日：2007-12-28

申请人： Yoshifumi Ikenaga ,  Masahiro Nomura

发明人： Yoshifumi Ikenaga ,  Masahiro Nomura

IPC分类号： G05F1/10

CPC分类号： H03K19/0016

摘要： A semiconductor integrated circuit device includes: a target circuit whose at least power supply voltage is variable; a power supply voltage providing circuit feeding the target circuit with a power supply voltage; and a minimum energy point monitor circuit detecting an energy-minimizing power supply voltage which minimizes a change in the energy consumed by the target circuit upon a change in the power supply voltage. The power supply voltage delivered by the power supply voltage providing circuit is controlled so as to be equal to the energy-minimizing power supply voltage detected by the minimum energy point monitor circuit.

摘要翻译： 一种半导体集成电路器件，包括：目标电路，其至少电源电压是可变的; 电源电压提供电路，向目标电路馈送电源电压; 以及最小能量点监视电路，其检测能量最小化电源电压，其使得在电源电压变化时使目标电路消耗的能量的变化最小化。 由电源电压提供电路输送的电源电压被控制为等于由最小能量点监控电路检测到的能量最小化电源电压。

公开(公告)号：US20100327961A1

公开(公告)日：2010-12-30

申请号：US12521605

申请日：2007-12-28

申请人： Yoshifumi Ikenaga ,  Masahiro Nomura

发明人： Yoshifumi Ikenaga ,  Masahiro Nomura

IPC分类号： G05F1/10

CPC分类号： H03K19/0016

摘要： A semiconductor integrated circuit device includes: a target circuit whose at least power supply voltage is variable; a power supply voltage providing circuit feeding the target circuit with a power supply voltage; and a minimum energy point monitor circuit detecting an energy-minimizing power supply voltage which minimizes a change in the energy consumed by the target circuit upon a change in the power supply voltage. The power supply voltage delivered by the power supply voltage providing circuit is controlled so as to be equal to the energy-minimizing power supply voltage detected by the minimum energy point monitor circuit.

摘要翻译： 一种半导体集成电路器件，包括：目标电路，其至少电源电压是可变的; 电源电压提供电路，向目标电路馈送电源电压; 以及最小能量点监视电路，其检测能量最小化电源电压，其使得在电源电压变化时使目标电路消耗的能量的变化最小化。 由电源电压提供电路输送的电源电压被控制为等于由最小能量点监控电路检测到的能量最小化电源电压。

公开(公告)号：US07719043B2

公开(公告)日：2010-05-18

申请号：US11632352

申请日：2005-07-04

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/7851

摘要： The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.

摘要翻译： 本发明涉及一种半导体器件，其包括具有从衬底平面突出的突出半导体层的鳍型场效应晶体管（FET），形成为跨越突出半导体层的栅极电极，栅极电极 所述突出半导体层以及设置在所述突出半导体层中的源极和漏极区域，其中所述半导体器件在半导体衬底上具有具有鳍型FET的元件形成区域，设置在所述半导体衬底上的沟槽，用于将所述元件形成区域 来自另一个元件形成区域，以及沟槽中的元件隔离绝缘膜; 元件形成区域具有通过挖掘到比沟槽的底表面浅的深度而比半导体衬底的上表面更深的深浅的衬底平坦表面，从衬底平坦表面突出并形成的半导体凸起部分 的半导体衬底，以及在浅衬底平面上的绝缘膜; 并且鳍式FET的突出半导体层由从半导体凸起部分的绝缘膜突出的部分形成。

公开(公告)号：US07701018B2

公开(公告)日：2010-04-20

申请号：US10593300

申请日：2005-03-22

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

IPC分类号： H01L27/088

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681 ,  H01L2029/7858

摘要： A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

摘要翻译： 一种包括第一半导体区域和第二半导体区域的半导体器件，（a）其中场效应晶体管由包括从衬底向上突出的至少一个半导体层的第一半导体区域，栅电极， 通过绝缘膜形成，使得栅电极跨越设置在栅电极两侧的半导体层中的半导体层和源极/漏极区，由此沟道区是 形成在所述半导体层的至少两侧，（b），其中所述第二半导体区域包括从所述衬底向上突出的半导体层，并且至少相对于与沟道垂直的方向的两端处的所述第一半导体区域相对 电流方向和面对第一半导体区域的半导体层的侧表面平行于沟道电流方向。

公开(公告)号：US20090032148A1

公开(公告)日：2009-02-05

申请号：US11909724

申请日：2006-03-30

申请人： Shinji Kozuma ,  Masahiro Nomura ,  Ikuro Hashimoto

发明人： Shinji Kozuma ,  Masahiro Nomura ,  Ikuro Hashimoto

IPC分类号： C22C38/54

CPC分类号： C21D9/46 ,  C22C38/00 ,  C22C38/06 ,  C22C38/58 ,  C23C22/12 ,  C23G1/08 ,  Y10T428/12979 ,  Y10T428/12993 ,  Y10T428/26

摘要： There is provided a high-strength hot rolled steel sheet excellent in phosphatability, wherein a maximum depth (Ry) of pits and bumps, existing on a surface thereof, is not less than 10 μm, and an average interval (Sm) of the pits and the bumps is not more than 30 μm, meeting either a requirement for a load length ratio (tp40) of the pits and the bumps on the surface at not more than 20%, or a requirement for a difference between a load length ratio (tp60) and the load length ratio (tp40), at not less than 60%, or both thereof. The high-strength hot rolled steel sheet is capable of exhibiting stable and excellent phosphatability even if Mo highly effective for reinforcement in strength is added thereto in expectation of a higher strength.

摘要翻译： 提供了优异的磷酸盐性的高强度热轧钢板，其表面上存在的凹坑和凸块的最大深度（Ry）不小于10μm，凹坑的平均间隔（Sm） 并且凸起不大于30μm，满足凹坑的负载长度比（tp40）和表面上的凸块的要求不大于20％，或者要求负载长度比（ tp60）和负载长度比（tp40），不小于60％，或其两者。 高强度热轧钢板即使在强度高的情况下也能够高效地加强强化，能够表现出稳定且优异的磷酸化性。