公开(公告)号：US10068909B1

公开(公告)日：2018-09-04

申请号：US15795270

申请日：2017-10-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Chien-Hung Chen

IPC: G11C11/412 ,  G11C11/40 ,  H01L27/11 ,  H01L27/02 ,  H01L23/528 ,  G11C11/419 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088

Abstract: The present invention provides a layout pattern of a memory device composed of static random access memory (SRAM), comprising four memory units located on a substrate, each memory unit being located in a non-rectangular region, the four non-rectangular regions combine a rectangular region, wherein each memory unit comprises a first inverter comprising a first pull-up transistor (PL1) and a first pull-down transistor (PD1), a second inverter comprises a second pull-up transistor (PL2) and a second pull-down transistor (PD2), an access transistor (PG) and a switching transistor (SW), wherein the source of the PG is coupled to an input terminal of the first inverter and a drain of the SW, a source of the SW is coupled to an output of the second inverter, wherein the PD1, the PD2, the SW, and the PG comprise a first diffusion region, the PL1 and the PL2 comprise a second diffusion region.

公开(公告)号：US10026726B2

公开(公告)日：2018-07-17

申请号：US15604685

申请日：2017-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L21/8238 ,  H01L21/768 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L27/02

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

公开(公告)号：US10020049B1

公开(公告)日：2018-07-10

申请号：US15413436

申请日：2017-01-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Chih-Wei Tsai

IPC: G11C11/419 ,  G11C11/418

Abstract: The present invention provides a six transistor static random-access memory (6T-SRAM) cell, the 6T-SRAM cell includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node, a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor, a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, and an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor.

公开(公告)号：US20180190344A1

公开(公告)日：2018-07-05

申请号：US15413436

申请日：2017-01-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Chih-Wei Tsai

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/418

Abstract: The present invention provides a six transistor static random-access memory (6T-SRAM) cell, the 6T-SRAM cell includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node, a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor, a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, and an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor.

公开(公告)号：US09953988B2

公开(公告)日：2018-04-24

申请号：US15635165

申请日：2017-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L21/336 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US20170373073A1

公开(公告)日：2017-12-28

申请号：US15686169

申请日：2017-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US20170263597A1

公开(公告)日：2017-09-14

申请号：US15604685

申请日：2017-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L27/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/768 ,  H01L27/11 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

公开(公告)号：US09761302B1

公开(公告)日：2017-09-12

申请号：US15092613

申请日：2016-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Yu Lu ,  Chang-Hung Chen ,  Chun-Hsien Huang ,  Han-Tsun Wang ,  Jheng-Tai Yan ,  Yu-Tse Kuo

IPC: G11C11/34 ,  G11C11/417 ,  G11C11/412 ,  H01L27/105

CPC classification number: G11C11/417 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1104

Abstract: A SRAM cell includes a first pass-gate device and a second-pass gate device comprising a first conductivity type, a first pull-down device and a second pull-down device comprising the first conductivity type, and a first pull-up device and a second pull-up device comprising a second conductivity type complementary to the first conductivity type. The first pass-gate device and the second pass-gate device respectively include first lightly-doped drains (hereinafter abbreviated as LDDs. The first pull-down device and the second pull-down device respectively include second LDDs. And a dosage of the first LDDs is different from a dosage of the second LDDs.

公开(公告)号：US09728541B1

公开(公告)日：2017-08-08

申请号：US15185043

申请日：2016-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L21/336 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US09401366B1

公开(公告)日：2016-07-26

申请号：US14792636

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Yu Lu ,  Chang-Hung Chen ,  Yu-Tse Kuo ,  Chun-Hsien Huang

IPC: G11C11/00 ,  H01L27/088 ,  H01L27/11 ,  H01L27/02 ,  H01L29/06 ,  G11C11/412 ,  H01L21/84 ,  H01L27/105 ,  H01L29/423

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/4125 ,  H01L21/845 ,  H01L27/1052 ,  H01L29/42392

Abstract: The present invention provides a layout pattern of an 8-transistor static random access memory (8T-SRAM), at least including a first diffusion region, a second diffusion region and a third diffusion region disposed on a substrate, a critical dimension region being disposed between the first diffusion region and the third diffusion region. The critical dimension region directly contacts the first diffusion region and the third diffusion region, a first extra diffusion region, a second extra diffusion region and a third extra diffusion region disposed surrounding and directly contacting the first diffusion region, the second diffusion region and the third diffusion region respectively. The first, the second and the third extra diffusion region are not disposed within the critical dimension region.

Abstract translation: 本发明提供了至少包括第一扩散区域，第二扩散区域和设置在衬底上的第三扩散区域的8-晶体管静态随机存取存储器（8T-SRAM）的布局图案，设置临界尺寸区域 在第一扩散区域和第三扩散区域之间。 临界尺寸区域直接接触第一扩散区域和第三扩散区域，第一额外扩散区域，第二额外扩散区域和设置在第一扩散区域，第二扩散区域和第三扩散区域周围并直接接触的第三额外扩散区域 扩散区。 第一，第二和第三附加扩散区域不设置在临界尺寸区域内。