公开(公告)号：US20210242282A1

公开(公告)日：2021-08-05

申请号：US17235785

申请日：2021-04-20

Applicant: United Microelectronics Corp.

Inventor： Chung-Tse Chen ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L27/24 ,  H01L45/00

Abstract: A method for fabricating memory device is provided. The method includes forming a transistor on a substrate. Further, a contact structure is formed on a source/drain region of the transistor. A conductive layer is formed on the contact structure. Four memory structures are formed on the conductive layer to form a quadrilateral structure.

公开(公告)号：US11024672B2

公开(公告)日：2021-06-01

申请号：US16418770

申请日：2019-05-21

Applicant: United Microelectronics Corp.

Inventor： Chung-Tse Chen ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L27/24 ,  H01L45/00

Abstract: A structure of memory device is provided. The structure of memory device includes a transistor formed on a substrate. A contact structure is disposed on a source/drain region of the transistor. A conductive layer is disposed on the contact structure. Four memory structures is disposed on the conductive layer to form a quadrilateral structure.

公开(公告)号：US20200328255A1

公开(公告)日：2020-10-15

申请号：US16418770

申请日：2019-05-21

Applicant: United Microelectronics Corp.

Inventor： Chung-Tse Chen ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L27/24 ,  H01L45/00

Abstract: A structure of memory device is provided. The structure of memory device includes a transistor formed on a substrate. A contact structure is disposed on a source/drain region of the transistor. A conductive layer is disposed on the contact structure. Four memory structures is disposed on the conductive layer to form a quadrilateral structure.

公开(公告)号：US20180108837A1

公开(公告)日：2018-04-19

申请号：US15359975

申请日：2016-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Liang Yi ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146

Abstract: A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.

公开(公告)号：US09923028B1

公开(公告)日：2018-03-20

申请号：US15402630

申请日：2017-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

CPC classification number: H01L27/2463 ,  H01L23/528 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608 ,  H05K999/99

Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

公开(公告)号：US20180033961A1

公开(公告)日：2018-02-01

申请号：US15260754

申请日：2016-09-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chia-Ching Hsu ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (ReRAM) cell structure, and an upper metal layer. The bottom metal layer is located above the substrate. The ReRAM cell structure is formed on the bottom metal layer. The ReRAM cell structure includes a bottom electrode, a memory cell layer, a top electrode, and a spacer. The memory cell layer is formed on the bottom electrode. The top electrode is formed on the memory cell layer. The spacer is formed on two sides of the bottom electrode, the memory cell layer and the top electrode. The upper metal layer is electrically connected to and directly contacting the top electrode.

公开(公告)号：US09799705B1

公开(公告)日：2017-10-24

申请号：US15297164

申请日：2016-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chia-Ching Hsu ,  Shen-De Wang ,  Ko-Chi Chen ,  Guoan Du

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/768

CPC classification number: H01L27/2436 ,  H01L21/76877 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

Abstract: The present invention provides a semiconductor device. The semiconductor device includes a contact structure disposed in a first dielectric layer, a second dielectric layer disposed on the first dielectric layer and having an opening disposed therein, a spacer disposed in the opening and partially covering the contact structure, and a resistive random-access memory (RRAM) disposed on the contact structure and directly contacting the spacer, wherein the RRAM includes a bottom electrode, a top electrode, and a switching resistance layer disposed between the bottom electrode and the top electrode.

公开(公告)号：US09659948B2

公开(公告)日：2017-05-23

申请号：US14856577

申请日：2015-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/11529 ,  H01L27/11573 ,  H01L27/11531

CPC classification number: H01L27/11529 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate with a memory region and a logic region, a logic gate stack, and a non-volatile gate stack. The substrate has a recess disposed in the memory region. The logic gate stack is disposed in the logic region and has a first top surface. The non-volatile gate stack is disposed in the recess and has a second top surface. The second top surface is lower than the first top surface by a step height.

公开(公告)号：US09595588B1

公开(公告)日：2017-03-14

申请号：US15069331

申请日：2016-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/42336 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11531

Abstract: A semiconductor device with embedded cell is provided. A silicon substrate has a first area with at least one first cell and a second area with at least one second cell. The first cell is positioned in the first area and formed in a trench of the silicon substrate, and the second cell is positioned in the second area and formed on the silicon substrate. The first cell includes a first dielectric layer formed on sidewalls and a bottom of the trench, a floating gate formed on the first dielectric layer and embedded in the trench, a second dielectric layer formed on the floating gate and embedded in the trench, and a control gate formed on the second dielectric layer and embedded in the trench, wherein the control gate is separated from the floating gate by the second dielectric layer.

Abstract translation: 提供具有嵌入式单元的半导体器件。 硅衬底具有具有至少一个第一单元的第一区域和具有至少一个第二单元的第二区域。 第一单元被定位在第一区域中并形成在硅衬底的沟槽中，并且第二单元被定位在第二区域中并形成在硅衬底上。 第一单元包括形成在沟槽的侧壁和底部上的第一介电层，形成在第一介电层上并嵌入在沟槽中的浮置栅极，形成在浮置栅极上并嵌入沟槽中的第二介电层，以及 控制栅极形成在第二介电层上并嵌入在沟槽中，其中控制栅极通过第二介电层与浮置栅极分离。

公开(公告)号：US09589977B1

公开(公告)日：2017-03-07

申请号：US14963833

申请日：2015-12-09

Applicant: United Microelectronics Corp.

Inventor： Ko-Chi Chen ,  Shen-De Wang

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28088 ,  H01L21/28282 ,  H01L29/408 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: The invention provides a non-volatile memory and a fabricating method thereof. The non-volatile memory includes a substrate, an embedded-type charge storage transistor, and a selection transistor. The substrate has an opening. The embedded-type charge storage transistor is disposed in the substrate. The embedded-type charge storage transistor includes a charge storage structure and a conductive layer. The charge storage structure is disposed on the substrate in the opening. The conductive layer is disposed on the charge storage structure and fills the opening. The selection transistor is disposed on the substrate at one side of the embedded-type charge storage transistor, wherein the selection transistor includes a metal gate structure. The non-volatile memory has excellent charge storage capacity.

Abstract translation: 本发明提供了一种非易失性存储器及其制造方法。 非易失性存储器包括衬底，嵌入式电荷存储晶体管和选择晶体管。 基板有开口。 嵌入式电荷存储晶体管设置在基板中。 嵌入式电荷存储晶体管包括电荷存储结构和导电层。 电荷存储结构设置在开口中的基板上。 导电层设置在电荷存储结构上并填充开口。 选择晶体管设置在嵌入式电荷存储晶体管的一侧的衬底上，其中选择晶体管包括金属栅极结构。 非易失性存储器具有优异的电荷存储容量。