公开(公告)号：US11251187B2

公开(公告)日：2022-02-15

申请号：US15712151

申请日：2017-09-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Chia-Chen Wu ,  Kai-Jiun Chang ,  Yi-An Huang ,  Tsun-Min Cheng

IPC: H01L27/108

Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

公开(公告)号：US10804365B2

公开(公告)日：2020-10-13

申请号：US15985730

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chun-Chieh Chiu ,  Pin-Hong Chen ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chia-Chen Wu ,  Tzu-Hao Liu

IPC: H01L21/02 ,  H01L29/49 ,  H01L27/108 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L21/285

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

公开(公告)号：US10707214B2

公开(公告)日：2020-07-07

申请号：US15990837

申请日：2018-05-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Chen Wu ,  Yi-Wei Chen ,  Chi-Mao Hsu ,  Kai-Jiun Chang ,  Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tsun-Min Cheng ,  Yi-An Huang

IPC: H01L27/108 ,  C23C14/06 ,  C23C14/34 ,  C23C14/58 ,  H01L21/285

Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.

公开(公告)号：US10672774B2

公开(公告)日：2020-06-02

申请号：US15900800

申请日：2018-02-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Pin-Hong Chen ,  Tsun-Min Cheng ,  Chun-Chieh Chiu

IPC: H01L27/108 ,  H01L21/285 ,  H01L21/3215 ,  H01L23/532

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.

公开(公告)号：US20190318933A1

公开(公告)日：2019-10-17

申请号：US15986797

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Hao Liu ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Po-Chih Wu ,  Pin-Hong Chen ,  Chun-Chieh Chiu ,  Tzu-Chieh Chen ,  Chih-Chien Liu ,  Chih-Chieh Tsai ,  Ji-Min Lin

IPC: H01L21/28 ,  H01L27/108 ,  G11C11/4097

Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

公开(公告)号：US20190013320A1

公开(公告)日：2019-01-10

申请号：US15986780

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chieh Chen ,  Pin-Hong Chen ,  Chih-Chieh Tsai ,  Chia-Chen Wu ,  Yi-An Huang ,  Kai-Jiun Chang ,  Tsun-Min Cheng ,  Yi-Wei Chen

IPC: H01L27/108 ,  H01L23/31

Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.

公开(公告)号：US09859123B1

公开(公告)日：2018-01-02

申请号：US15472308

申请日：2017-03-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Chen Wu ,  Pin-Hong Chen ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/321 ,  H01L29/66

CPC classification number: H01L21/28518 ,  H01L21/321 ,  H01L21/76889 ,  H01L29/665

Abstract: A method for fabricating a semiconductor device is disclosed. A substrate having a conductive region is provided. A metal layer is deposited on the conductive region. The metal layer reacts with the conductive region to form a first metal silicide layer. A TiN layer is deposited on the metal layer. A SiN layer is deposited on the TiN layer. An annealing process is performed to convert the first metal silicide layer into a second metal silicide layer.

公开(公告)号：US20170236747A1

公开(公告)日：2017-08-17

申请号：US15586240

申请日：2017-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

公开(公告)号：US09679813B2

公开(公告)日：2017-06-13

申请号：US14710583

申请日：2015-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

公开(公告)号：US20170117379A1

公开(公告)日：2017-04-27

申请号：US14924532

申请日：2015-10-27

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.