公开(公告)号：US20170338239A1

公开(公告)日：2017-11-23

申请号：US15161419

申请日：2016-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Wang Xiang ,  Yi-Shan Chiu

IPC: H01L27/11582 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L29/40117 ,  H01L29/4234

Abstract: A semiconductor structure includes a substrate and a plurality of memory cells disposed on the substrate. Each memory cell includes a gate structure. The gate structures are spaced from each other by a spacing S. Each gate structure includes a dielectric layer and a gate electrode. The dielectric layer has an U-shape and defines an opening toward upside. The gate electrode is disposed in the opening. Each gate structure has a length L. A ratio of S/L is smaller than 1.

公开(公告)号：US12156487B2

公开(公告)日：2024-11-26

申请号：US18382055

申请日：2023-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H10N70/00 ,  H10B63/00

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.

公开(公告)号：US12010931B2

公开(公告)日：2024-06-11

申请号：US17196979

申请日：2021-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H01L45/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/841 ,  H10B63/845 ,  H10N70/021 ,  H10N70/066 ,  H10N70/8833

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.

公开(公告)号：US20240057488A1

公开(公告)日：2024-02-15

申请号：US18382055

申请日：2023-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/841 ,  H10B63/845 ,  H10N70/021 ,  H10N70/066 ,  H10N70/8833

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.

公开(公告)号：US11387337B2

公开(公告)日：2022-07-12

申请号：US17134131

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Shen-De Wang ,  Chia-Ching Hsu ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/792

Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

公开(公告)号：US20200043791A1

公开(公告)日：2020-02-06

申请号：US16116730

申请日：2018-08-29

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Wei Ta ,  Ling-Gang Fang ,  Shang Xue

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.

公开(公告)号：US10312249B2

公开(公告)日：2019-06-04

申请号：US15808019

申请日：2017-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Chuan Sun ,  Wei Ta ,  Wang Xiang

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/266 ,  H01L29/788

Abstract: A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.

公开(公告)号：US09978758B1

公开(公告)日：2018-05-22

申请号：US15613103

申请日：2017-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Wei Ta ,  Chuan Sun

IPC: H01L27/115 ,  H01L29/423 ,  H01L27/11517 ,  H01L21/283 ,  H01L21/02

CPC classification number: H01L21/0214 ,  H01L21/28282 ,  H01L21/283 ,  H01L27/11568 ,  H01L29/42344

Abstract: A flash memory includes a substrate, a memory gate on the substrate, a charge-storage layer between the memory gate and the substrate, a select gate adjacent to the memory gate, a select gate dielectric layer between the select gate and the substrate, a first oxide-nitride spacer between the memory gate and the select gate, and a second oxide-nitride spacer. The select gate includes an upper portion and a lower portion. The second oxide-nitride spacer is disposed between the first oxide-nitride spacer and the upper portion of the select gate.