公开(公告)号：US20140327055A1

公开(公告)日：2014-11-06

申请号：US13886382

申请日：2013-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Cheng-Guo Chen ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chung-Fu Chang

IPC: H01L21/28 ,  H01L29/40

CPC classification number: H01L29/42364 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7851

Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Abstract translation: 公开了替代浇口工艺。 提供了一种在基板上形成的基板和虚拟栅极结构，其中，虚设栅极结构包括基板上的虚设层，虚设层上的硬掩模层，虚设层两侧的间隔物和硬掩模层， 以及覆盖衬底，间隔物和硬掩模层的接触蚀刻停止层（CESL）。 垫片和CESL由相同的材料制成。 然后，去除CESL的顶部以露出硬掩模层。 接下来，去除硬掩模层。 之后，去除虚拟层以形成沟槽。

公开(公告)号：US09196542B2

公开(公告)日：2015-11-24

申请号：US13899581

申请日：2013-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin

IPC: H01L21/8234 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823468 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer.

Abstract translation: 提供一种制造半导体器件的方法。 形成第一堆叠结构和第二堆叠结构以分别覆盖第一鳍结构和第二鳍结构的一部分。 随后，通过原子层沉积工艺分别在翅片结构的侧壁上形成间隔物，间隔物的组成包括硅氮化硅。 之后，形成并蚀刻层间电介质，以露出硬掩模层。 形成掩模层以覆盖第二堆叠结构和介电层的一部分。 之后，在掩模层的覆盖下去除第一堆叠结构中的硬掩模层。 然后，第一堆叠结构中的虚设层被导电层代替。

公开(公告)号：US09196500B2

公开(公告)日：2015-11-24

申请号：US13859720

申请日：2013-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Chien-Ting Lin

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/3086 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/66795

Abstract: A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate.

Abstract translation: 一种用于制造半导体结构的方法，包括提供具有多个心轴图案和多个虚拟图案的基板，同时在心轴图案的侧壁上形成多个第一间隔件，在虚设图案的侧壁上形成多个第二间隔件，以及 移除第二间隔件和心轴图案以在基底上形成多个间隔图案。

公开(公告)号：US09013003B2

公开(公告)日：2015-04-21

申请号：US13728948

申请日：2012-12-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/336 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/823468 ,  H01L21/02068 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/165 ,  H01L29/4232 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract translation: 半导体结构包括第一栅极和第二栅极，第一间隔物和第二间隔物，两个第一外延结构和两个第二外延结构。 第一栅极和第二栅极位于基板上。 第一间隔物和第二间隔物分别位于第一栅极和第二栅极旁边的衬底上。 第一外延结构和第二外延结构分别位于第一间隔物和第二间隔物旁边的衬底中，其中第一间隔物和第二间隔物具有不同的厚度，并且第一外延结构之间的间隔不同于 第二外延结构。 此外，本发明还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US20140349452A1

公开(公告)日：2014-11-27

申请号：US13899581

申请日：2013-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin

IPC: H01L21/8234

CPC classification number: H01L21/823468 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer.

Abstract translation: 提供一种制造半导体器件的方法。 形成第一堆叠结构和第二堆叠结构以分别覆盖第一鳍结构和第二鳍结构的一部分。 随后，通过原子层沉积工艺分别在翅片结构的侧壁上形成间隔物，间隔物的组成包括硅氮化硅。 之后，形成并蚀刻层间电介质，以露出硬掩模层。 形成掩模层以覆盖第二堆叠结构和介电层的一部分。 之后，在掩模层的覆盖下去除第一堆叠结构中的硬掩模层。 然后，第一堆叠结构中的虚设层被导电层代替。

公开(公告)号：US20140213028A1

公开(公告)日：2014-07-31

申请号：US13756464

申请日：2013-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao

IPC: H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823468 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An epitaxial process includes the following steps. A substrate including a first area and a second area is provided. A first gate and a second gate are formed respectively on the substrate of the first area and the second area. A first spacer and a second spacer are respectively formed on the substrate beside the first gate and the second gate at the same time. A first epitaxial structure is formed beside the first spacer and then a second epitaxial structure is formed beside the second spacer by the first spacer and the second spacer respectively.

Abstract translation: 外延工艺包括以下步骤。 提供了包括第一区域和第二区域的基板。 第一栅极和第二栅极分别形成在第一区域和第二区域的基板上。 第一间隔物和第二间隔物同时分别形成在第一栅极和第二栅极旁边的基板上。 在第一间隔物旁边形成第一外延结构，然后通过第一间隔物和第二间隔物分别在第二间隔物旁边形成第二外延结构。

公开(公告)号：US20140205953A1

公开(公告)日：2014-07-24

申请号：US13747421

申请日：2013-01-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Po-Chao Tsao ,  Chia-Jui Liang ,  En-Chiuan Liou

IPC: G03F7/20

CPC classification number: H01L21/0274 ,  G03F7/0035 ,  H01L21/0337

Abstract: A method for forming a semiconductor device comprises the following steps: first, a substrate is provided, a first photo-etching process is carried out with a first photomask to form at least one device structure and a plurality of compensation structures, wherein the first photomask comprises at least one device pattern and a plurality of dummy patterns. A photoresist layer is then formed on the device structure and each compensation structures; a second photo-etching process is then carried out with a second photomask to remove each compensation structure.

Abstract translation: 一种用于形成半导体器件的方法包括以下步骤：首先，提供衬底，利用第一光掩模进行第一光蚀刻工艺以形成至少一个器件结构和多个补偿结构，其中第一光掩模 包括至少一个设备图案和多个虚设图案。 然后在器件结构和每个补偿结构上形成光致抗蚀剂层; 然后用第二光掩模执行第二光蚀刻工艺以去除每个补偿结构。

公开(公告)号：US20140191358A1

公开(公告)日：2014-07-10

申请号：US13736082

申请日：2013-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract translation: 提供浅沟槽隔离（STI）及其形成方法。 STI结构包括上绝缘部分和下绝缘部分，其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层，上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 缓冲层的一部分在第一绝缘体和第二绝缘体之间接合，缓冲层的外侧壁和第一绝缘体的侧壁平整。