公开(公告)号：US20170179306A1

公开(公告)日：2017-06-22

申请号：US14995174

申请日：2016-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L29/872 ,  H01L29/06

CPC classification number: H01L29/8725 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/872

Abstract: A semiconductor device include a substrate, a first well region formed in the substrate, a first isolation structure formed in the first well region, a Schottky barrier structure formed on the first well region, and a plurality of assist structures formed on the first well region. The substrate includes a first conductivity type, the first well region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The assist structures physically contact the first well region.

公开(公告)号：US20170125547A1

公开(公告)日：2017-05-04

申请号：US15406355

申请日：2017-01-13

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L29/66492 ,  H01L21/2652 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of forming a semiconductor device is provided. At least two shallow trenches are formed in a substrate. An insulating layer is formed on surfaces of the substrate and the shallow trenches. A conductive layer is formed on the substrate between the shallow trenches. At least one spacer is formed on a sidewall of the conductive layer, wherein the spacer fills up each shallow trench.

公开(公告)号：US20170062279A1

公开(公告)日：2017-03-02

申请号：US14835700

申请日：2015-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sih-Yun Wei ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L21/8238 ,  H01L21/266 ,  H01L27/092 ,  H01L29/66 ,  H01L21/265 ,  H01L29/167

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/6659

Abstract: A transistor set forming process includes the following steps. A substrate having a first area and a second area is provided. An implantation process is performed to form a diffusion region of a first transistor in the substrate of the first area and a channel region of a second transistor in the substrate of the second area at the same time.

Abstract translation: 晶体管组形成工艺包括以下步骤。 提供具有第一区域和第二区域的衬底。 执行注入工艺，以在第一区域的衬底中的第一晶体管的扩散区域和第二区域的衬底中的第二晶体管的沟道区域同时形成。

公开(公告)号：US09583617B2

公开(公告)日：2017-02-28

申请号：US14737186

申请日：2015-06-11

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/70 ,  H01L29/78

CPC classification number: H01L29/66492 ,  H01L21/2652 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

Abstract: Provided is a semiconductor device including a substrate, an insulating layer, a conductive layer and at least one spacer. The substrate has at least two shallow trenches therein. The conductive layer is disposed on the substrate between the shallow trenches. The insulating layer is disposed between the substrate and the conductive layer. The at least one spacer is disposed on one sidewall of the conductive layer and fills up each shallow trench. A method of forming a semiconductor device is further provided.

Abstract translation: 提供了一种半导体器件，其包括衬底，绝缘层，导电层和至少一个间隔物。 衬底中具有至少两个浅沟槽。 导电层设置在浅沟槽之间的衬底上。 绝缘层设置在基板和导电层之间。 至少一个间隔件设置在导电层的一个侧壁上并填充每个浅沟槽。 还提供了形成半导体器件的方法。

公开(公告)号：US12224335B2

公开(公告)日：2025-02-11

申请号：US17867640

申请日：2022-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chung Yang

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L29/78

Abstract: A semiconductor device includes a substrate of first conductivity type; a first heavily doped region and a second heavily doped region of second conductivity type spaced apart from the first heavily doped region, located in the substrate; a channel region in the substrate and between the first heavily doped region and the second heavily doped region; a gate disposed on the channel region; a hard mask layer covering a top surface and a sidewall of the gate; and a spacer disposed on a sidewall of the hard mask layer.

公开(公告)号：US20250031438A1

公开(公告)日：2025-01-23

申请号：US18908700

申请日：2024-10-07

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Wen-Fang Lee

IPC: H01L27/085

Abstract: A semiconductor structure includes a substrate comprising a first well region of a first conductive type, a second well region of a second conductive type, and a junction between the first well region and the second well region, wherein the first conductive type and the second conductive type are complementary. An isolation structure is formed in the substrate to define a plurality of first dummy diffusions and second dummy diffusions and at least a first active region in the first well region, wherein the first dummy diffusions are adjacent to the junction, the first dummy diffusions are between the second dummy diffusions and the first active region, and wherein the second dummy diffusions respectively comprise a metal silicide portion. A plurality of first dummy gates are disposed on the first dummy diffusions and completely cover the first dummy diffusions, respectively.

公开(公告)号：US20230352478A1

公开(公告)日：2023-11-02

申请号：US18218578

申请日：2023-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Wen-Fang Lee

IPC: H01L27/085

CPC classification number: H01L27/085

Abstract: A semiconductor structure comprises a substrate having a first well region of a first conductive type, a second well region of a second conductive type, and a junction between the first well region and the second well region. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures and second dummy structures and at least a first active region are defined in the first well region by an isolation structure. The first dummy structures are adjacent to the junction and respectively comprise a first metal silicide region and a first doped region of the first conductive type and between the first metal silicide region and the first well region. The first dummy structures are between the second dummy structures and the junction. The second dummy structures respectively comprise a second metal silicide region that direct contacts the first well region.

公开(公告)号：US20230326801A1

公开(公告)日：2023-10-12

申请号：US18335154

申请日：2023-06-15

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/02 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8249 ,  H01L29/423

CPC classification number: H01L21/823425 ,  H01L29/0607 ,  H01L27/0251 ,  H01L29/4925 ,  H01L29/7832 ,  H01L21/8249 ,  H01L29/7835 ,  H01L21/823437 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/78

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

公开(公告)号：US11735586B2

公开(公告)日：2023-08-22

申请号：US17163544

申请日：2021-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Wen-Fang Lee

IPC: H01L27/085

CPC classification number: H01L27/085

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, a first well region of a first conductive type and a second well region of a second conductive type disposed in the substrate. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures are disposed in the first well region and arranged along a junction between the first well region and the second well region. The first dummy structures respectively include a first conductive region and a first doped region disposed between the first conductive region and the first doped region.

公开(公告)号：US20220208760A1

公开(公告)日：2022-06-30

申请号：US17163544

申请日：2021-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Wen-Fang Lee

IPC: H01L27/085

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, a first well region of a first conductive type and a second well region of a second conductive type disposed in the substrate. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures are disposed in the first well region and arranged along a junction between the first well region and the second well region. The first dummy structures respectively include a first conductive region and a first doped region disposed between the first conductive region and the first doped region.