公开(公告)号：US10600882B2

公开(公告)日：2020-03-24

申请号：US14880275

申请日：2015-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chun-Hsien Lin

IPC: H01L21/70 ,  H01L29/49 ,  H01L29/423

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein. The gate structure further includes a gate electrode with a protruding portion, and a gate dielectric layer disposed between the gate electrode and the substrate. A spacer is disposed between the interlayer dielectric and the gate electrode. An insulating cap layer is disposed atop the gate electrode and encompasses the top and the sidewall of the protruding portion.

公开(公告)号：US20200020792A1

公开(公告)日：2020-01-16

申请号：US16581750

申请日：2019-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L29/49

Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.

公开(公告)号：US20190267385A1

公开(公告)日：2019-08-29

申请号：US16406017

申请日：2019-05-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chun-Hsien Lin ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L29/49

Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.

公开(公告)号：US20180350937A1

公开(公告)日：2018-12-06

申请号：US16056564

申请日：2018-08-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device is disclosed. A dummy gate is formed on a semiconductor substrate. The dummy gate has a first sidewall and a second sidewall opposite to the first sidewall. A low-k dielectric layer is formed on the first sidewall of the dummy gate and the semiconductor substrate. A spacer material layer is deposited on the low-k dielectric layer, the second sidewall of the dummy gate, and the semiconductor substrate. The spacer material layer and the low-k dielectric layer are etched to form a first spacer structure on the first sidewall and a second spacer structure on the second sidewall. A drain doping region is formed in the semiconductor substrate adjacent to the first spacer structure. A source doping region is formed in the semiconductor substrate adjacent to the second spacer structure.

公开(公告)号：US10079290B2

公开(公告)日：2018-09-18

申请号：US15394833

申请日：2016-12-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7835 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A semiconductor device including a semiconductor substrate, agate on the semiconductor substrate, a drain doping region in the semiconductor substrate on a first side of the gate, a source doping region in the semiconductor substrate on a second side of the gate, a first spacer structure on a first sidewall of the gate between the gate and the drain doping region, and a second spacer structure on a second sidewall of the gate between the gate and the source doping region. The first spacer structure is composed of a low-k dielectric layer on the first sidewall of the gate and a first spacer material layer on the low-k dielectric layer. The second spacer structure is composed of a second spacer material layer on the second sidewall of the gate.

公开(公告)号：US10069009B2

公开(公告)日：2018-09-04

申请号：US15861700

申请日：2018-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L21/00 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L29/267 ,  H01L29/24 ,  H01L29/16 ,  H01L29/161 ,  H01L29/08 ,  H01L21/768 ,  H01L21/283 ,  H01L29/417 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7845

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first recess adjacent to two sides of the gate structure; forming an epitaxial layer in the first recess; removing part of the epitaxial layer to forma second recess; and forming an interlayer dielectric (ILD) layer on the gate structure and into the second recess.

公开(公告)号：US20170301670A1

公开(公告)日：2017-10-19

申请号：US15641336

申请日：2017-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Chun-Hsien Lin

IPC: H01L27/088 ,  H01L29/40 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/76819 ,  H01L21/76853 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/401 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US09748233B2

公开(公告)日：2017-08-29

申请号：US14873223

申请日：2015-10-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Chun-Hsien Lin

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/76819 ,  H01L21/76853 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/401 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US09666715B2

公开(公告)日：2017-05-30

申请号：US14599556

申请日：2015-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Chun-Hsien Lin ,  Chen-Yi Weng

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: A field effect transistor with epitaxial structures includes a fin-shaped structure and a metal gate across the fin-shaped structure. The metal gate includes a pair of recess regions disposed on two sides of the bottom of the metal gate.

公开(公告)号：US09406805B2

公开(公告)日：2016-08-02

申请号：US14749648

申请日：2015-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Rai-Min Huang ,  Sheng-Huei Dai ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L21/02 ,  H01L21/20

CPC classification number: H01L29/7853 ,  H01L21/02647 ,  H01L21/2022 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785 ,  H01L2029/7858

Abstract: A Fin-FET and a method of forming the Fin-FET are provided. A substrate is provided, and then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.