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    Integrated circuit and manufacturing method thereof
    25.
    发明授权
    Integrated circuit and manufacturing method thereof 有权

    公开(公告)号：US10249528B2

    公开(公告)日：2019-04-02

    申请号：US15681419

    申请日：2017-08-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chiu-Jung Chiu ,  Hung-Chan Lin ,  Yu-Chun Chen

    IPC: H01L21/762 ,  H01L21/02 ,  H01L27/06 ,  H01L21/768 ,  H01L29/94 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/28

    Abstract: An integrated circuit includes a first insulation layer, a bottom plate, a first patterned dielectric layer, a medium plate, a second patterned dielectric layer, and a top plate. The first patterned dielectric layer is disposed on the bottom plate. The medium plate is disposed on the first patterned dielectric layer. At least a part of the first patterned dielectric layer and the medium plate and a part of the bottom plate are disposed in a first trench penetrating the first insulation layer. The bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor. The second patterned dielectric layer is disposed on the medium plate. The top plate is disposed on the second patterned dielectric layer. The medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor. The bottom plate is electrically connected with the top plate.

    Array of dynamic random access memory cells
    26.
    发明授权
    Array of dynamic random access memory cells 有权

    公开(公告)号：US10032777B1

    公开(公告)日：2018-07-24

    申请号：US15613288

    申请日：2017-06-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Wen Chen ,  Chi-Chang Shuai ,  Hung-Chan Lin ,  Ting-Hao Chang ,  Hsien-Hung Tsai

    IPC: H01L27/108 ,  G06F12/0846

    Abstract: An array of dynamic random access memory cells includes a first set of memory cell pairs in a first row, a second set of memory cells in a second row, and a first set of bit line contacts in the first row. The second set of memory cell pairs are disposed adjacent to the first set of memory cell pairs, and each two of the memory cell pairs in the second row include a common S/D region. Each of the first set of bit line contacts is electrically coupled to each of the common S/D regions of the memory cell pairs in the second row respectively.

    Layout pattern of magnetoresistive random access memory
    28.
    发明授权
    Layout pattern of magnetoresistive random access memory 有权

    公开(公告)号：US12190926B2

    公开(公告)日：2025-01-07

    申请号：US18108025

    申请日：2023-02-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hung-Chan Lin ,  Jia-Rong Wu ,  Yi-Ting Wu

    IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10

    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region, a first gate pattern extending from the first cell region to the third cell region along a first direction, a first diffusion region extending from the first cell region to the second cell region along a second direction, a first metal pattern adjacent to one side of the first gate pattern and overlapping the first diffusion region, a source line pattern extending from the first cell region to the second cell region along the second direction, and a first spin orbit torque (SOT) pattern extending along the first direction and overlapping the first metal pattern and the source line pattern.

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