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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    25.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20180033961A1

    公开(公告)日：2018-02-01

    申请号：US15260754

    申请日：2016-09-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Liang Yi ,  Chia-Ching Hsu ,  Shen-De Wang ,  Ko-Chi Chen

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (ReRAM) cell structure, and an upper metal layer. The bottom metal layer is located above the substrate. The ReRAM cell structure is formed on the bottom metal layer. The ReRAM cell structure includes a bottom electrode, a memory cell layer, a top electrode, and a spacer. The memory cell layer is formed on the bottom electrode. The top electrode is formed on the memory cell layer. The spacer is formed on two sides of the bottom electrode, the memory cell layer and the top electrode. The upper metal layer is electrically connected to and directly contacting the top electrode.

    Semiconductor device with embedded cell and method of manufacturing the same
    28.
    发明授权
    Semiconductor device with embedded cell and method of manufacturing the same 有权
    具有嵌入式电池的半导体器件及其制造方法

    公开(公告)号：US09595588B1

    公开(公告)日：2017-03-14

    申请号：US15069331

    申请日：2016-03-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Sung Huang ,  Ko-Chi Chen ,  Shen-De Wang

    IPC: H01L29/788 ,  H01L29/423 ,  H01L27/115

    CPC classification number: H01L29/42336 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11531

    Abstract: A semiconductor device with embedded cell is provided. A silicon substrate has a first area with at least one first cell and a second area with at least one second cell. The first cell is positioned in the first area and formed in a trench of the silicon substrate, and the second cell is positioned in the second area and formed on the silicon substrate. The first cell includes a first dielectric layer formed on sidewalls and a bottom of the trench, a floating gate formed on the first dielectric layer and embedded in the trench, a second dielectric layer formed on the floating gate and embedded in the trench, and a control gate formed on the second dielectric layer and embedded in the trench, wherein the control gate is separated from the floating gate by the second dielectric layer.

    Abstract translation: 提供具有嵌入式单元的半导体器件。 硅衬底具有具有至少一个第一单元的第一区域和具有至少一个第二单元的第二区域。 第一单元被定位在第一区域中并形成在硅衬底的沟槽中，并且第二单元被定位在第二区域中并形成在硅衬底上。 第一单元包括形成在沟槽的侧壁和底部上的第一介电层，形成在第一介电层上并嵌入在沟槽中的浮置栅极，形成在浮置栅极上并嵌入沟槽中的第二介电层，以及 控制栅极形成在第二介电层上并嵌入在沟槽中，其中控制栅极通过第二介电层与浮置栅极分离。

    Non-volatile memory and fabricating method thereof
    29.
    发明授权
    Non-volatile memory and fabricating method thereof 有权
    非易失性存储器及其制造方法

    公开(公告)号：US09589977B1

    公开(公告)日：2017-03-07

    申请号：US14963833

    申请日：2015-12-09

    Applicant: United Microelectronics Corp.

    Inventor： Ko-Chi Chen ,  Shen-De Wang

    IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/28

    CPC classification number: H01L27/1157 ,  H01L21/28088 ,  H01L21/28282 ,  H01L29/408 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

    Abstract: The invention provides a non-volatile memory and a fabricating method thereof. The non-volatile memory includes a substrate, an embedded-type charge storage transistor, and a selection transistor. The substrate has an opening. The embedded-type charge storage transistor is disposed in the substrate. The embedded-type charge storage transistor includes a charge storage structure and a conductive layer. The charge storage structure is disposed on the substrate in the opening. The conductive layer is disposed on the charge storage structure and fills the opening. The selection transistor is disposed on the substrate at one side of the embedded-type charge storage transistor, wherein the selection transistor includes a metal gate structure. The non-volatile memory has excellent charge storage capacity.

    Abstract translation: 本发明提供了一种非易失性存储器及其制造方法。 非易失性存储器包括衬底，嵌入式电荷存储晶体管和选择晶体管。 基板有开口。 嵌入式电荷存储晶体管设置在基板中。 嵌入式电荷存储晶体管包括电荷存储结构和导电层。 电荷存储结构设置在开口中的基板上。 导电层设置在电荷存储结构上并填充开口。 选择晶体管设置在嵌入式电荷存储晶体管的一侧的衬底上，其中选择晶体管包括金属栅极结构。 非易失性存储器具有优异的电荷存储容量。

    Split gate non-volatile memory device and method for fabricating the same
    30.
    发明授权
    Split gate non-volatile memory device and method for fabricating the same 有权
    分闸非易失性存储器件及其制造方法

    公开(公告)号：US09379128B1

    公开(公告)日：2016-06-28

    申请号：US14809342

    申请日：2015-07-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Liang Yi ,  Ko-Chi Chen ,  Shen-De Wang ,  Chia-Ching Hsu ,  Chun-Sung Huang ,  Wen-Peng Hsu

    IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28 ,  H01L21/225

    CPC classification number: H01L27/11568 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

    Abstract: A split gate NVM device includes a semiconductor substrate, an ONO structure disposed on the semiconductor substrate, a first gate electrode disposed on the ONO structure, a second gate electrode disposed on the semiconductor substrate, adjacent to and insulated from the first gate electrode and the ONO structure, a first doping region with a first conductivity formed in the semiconductor substrate and adjacent to the ONO structure, a second doping region with the first conductivity formed in the semiconductor substrate and adjacent to the second gate electrode, and a third doping region with the first conductivity formed in the semiconductor substrate, disposed between the first doping region and the second doping region and adjacent to the ONO structure and the second gate electrode.

    Abstract translation: 分路门NVM器件包括半导体衬底，设置在半导体衬底上的ONO结构，设置在ONO结构上的第一栅电极，设置在半导体衬底上的第二栅极，与第一栅电极相邻并绝缘， ONO结构，在半导体衬底中形成并与ONO结构相邻的具有第一导电性的第一掺杂区，在半导体衬底中形成并与第二栅电极相邻的具有第一导电性的第二掺杂区，以及第三掺杂区， 所述第一导电体形成在所述半导体衬底中，设置在所述第一掺杂区域和所述第二掺杂区域之间并且邻近所述ONO结构和所述第二栅电极。

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