公开(公告)号：US10978589B2

公开(公告)日：2021-04-13

申请号：US16529523

申请日：2019-08-01

Applicant: United Microelectronics Corp.

Inventor： Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/66 ,  H01L29/165

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.

公开(公告)号：US20190067480A1

公开(公告)日：2019-02-28

申请号：US15721177

申请日：2017-09-29

Applicant: United Microelectronics Corp.

Inventor： Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.

公开(公告)号：US20180068998A1

公开(公告)日：2018-03-08

申请号：US15289988

申请日：2016-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ti Wang ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L27/082 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/082 ,  H01L27/0207 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0813 ,  H01L29/1008 ,  H01L29/407 ,  H01L29/735

Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.

公开(公告)号：US09853021B1

公开(公告)日：2017-12-26

申请号：US15614624

申请日：2017-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ti Wang ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L29/49 ,  H01L27/06 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L27/0617 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a shallow trench isolation (STI) adjacent to the first fin-shaped structure; and forming a gate structure on the first fin-shaped structure and the STI. Preferably, the gate structure comprises a left portion and the right portion and the work functions in the left portion and the right portion are different.

公开(公告)号：US20170243977A1

公开(公告)日：2017-08-24

申请号：US15064618

申请日：2016-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Yao Lin ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/167 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4236 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7848

Abstract: The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.

公开(公告)号：US08823109B2

公开(公告)日：2014-09-02

申请号：US13736951

申请日：2013-01-09

Applicant: United Microelectronics Corp.

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

Abstract translation: 在本发明中提供一种晶体管结构。 晶体管结构包括：包括N型阱的衬底，设置在N型阱上的栅极，设置在栅极上的间隔物，位于衬垫下方的衬底中的第一轻掺杂区域，P型源极/漏极 位于栅极两侧的衬底中的覆盖P型源/漏区和第一轻掺杂区的硅帽层和设置在硅帽层上的硅化物层，并且仅覆盖硅的一部分 盖层。