公开(公告)号：US09634002B1

公开(公告)日：2017-04-25

申请号：US15057079

申请日：2016-02-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Tsai ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L27/08 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L21/823468 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

公开(公告)号：US08823109B2

公开(公告)日：2014-09-02

申请号：US13736951

申请日：2013-01-09

Applicant: United Microelectronics Corp.

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

Abstract translation: 在本发明中提供一种晶体管结构。 晶体管结构包括：包括N型阱的衬底，设置在N型阱上的栅极，设置在栅极上的间隔物，位于衬垫下方的衬底中的第一轻掺杂区域，P型源极/漏极 位于栅极两侧的衬底中的覆盖P型源/漏区和第一轻掺杂区的硅帽层和设置在硅帽层上的硅化物层，并且仅覆盖硅的一部分 盖层。

公开(公告)号：US20130119479A1

公开(公告)日：2013-05-16

申请号：US13736951

申请日：2013-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

Abstract translation: 在本发明中提供一种晶体管结构。 晶体管结构包括：包括N型阱的衬底，设置在N型阱上的栅极，设置在栅极上的间隔物，位于衬垫下方的衬底中的第一轻掺杂区域，P型源极/漏极 位于栅极两侧的衬底中的覆盖P型源/漏区和第一轻掺杂区的硅帽层和设置在硅帽层上的硅化物层，并且仅覆盖硅的一部分 盖层。

公开(公告)号：US20230129579A1

公开(公告)日：2023-04-27

申请号：US17528159

申请日：2021-11-16

Applicant: United Microelectronics Corp.

Inventor： Hao-Ming Lee ,  Ta Kang Lo ,  Tsai-Fu Chen ,  Shou-Wei Hsieh

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

Abstract: A high electron mobility transistor (HEMT) device including a substrate, a channel layer, a barrier layer, a p-type gallium nitride (GaN) spacer, a gate electrode, a source electrode, and a drain electrode is provided. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer and has a protruding portion. The P-type GaN spacer is disposed on a side wall of the protruding portion. The gate electrode is disposed on the protruding portion and the P-type GaN spacer. The source electrode and the drain electrode are disposed on two sides of the gate electrode.

公开(公告)号：US09779998B2

公开(公告)日：2017-10-03

申请号：US15450037

申请日：2017-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Tsai ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823468 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

公开(公告)号：US20170221766A1

公开(公告)日：2017-08-03

申请号：US15450037

申请日：2017-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Tsai ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823468 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

公开(公告)号：US12100756B2

公开(公告)日：2024-09-24

申请号：US17528159

申请日：2021-11-16

Applicant: United Microelectronics Corp.

Inventor： Hao-Ming Lee ,  Ta Kang Lo ,  Tsai-Fu Chen ,  Shou-Wei Hsieh

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/0607 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7783 ,  H01L2924/13064

Abstract: A high electron mobility transistor (HEMT) device including a substrate, a channel layer, a barrier layer, a p-type gallium nitride (GaN) spacer, a gate electrode, a source electrode, and a drain electrode is provided. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer and has a protruding portion. The P-type GaN spacer is disposed on a side wall of the protruding portion. The gate electrode is disposed on the protruding portion and the P-type GaN spacer. The source electrode and the drain electrode are disposed on two sides of the gate electrode.

公开(公告)号：US09685520B1

公开(公告)日：2017-06-20

申请号：US15355032

申请日：2016-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shuo-Lin Hsu ,  Hsin-Ta Hsieh ,  Chun-Chia Chen ,  Chen-Chien Li ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66666

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.