-
公开(公告)号：US20240120419A1
公开(公告)日：2024-04-11
申请号：US18528806
申请日：2023-12-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ling-Chun Chou , Yu-Hung Chang , Kun-Hsien Lee
CPC classification number: H01L29/7823 , H01L29/0623
Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.
-
公开(公告)号：US11322215B1
公开(公告)日：2022-05-03
申请号：US17326375
申请日：2021-05-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Pin Tsao , Tsung-Hsun Wu , Liang-Wei Chiu , Kuo-Hsing Lee , Sheng-Yuan Hsueh , Kun-Hsien Lee , Chang-Chien Wong
Abstract: A one-time programmable (OTP) memory device includes a first memory cell, which further includes a first source line extending along a first direction on a substrate, a first word line extending along the first direction on one side of the first source line, a second word line extending along the first direction on another side of the first source line, a first diffusion region extending along a second direction adjacent to two sides of the first word line and the second word line, and a first metal interconnection connecting the first word line and the second word line.
-
公开(公告)号：US10439066B2
公开(公告)日：2019-10-08
申请号：US15721177
申请日：2017-09-29
Applicant: United Microelectronics Corp.
Inventor： Ling-Chun Chou , Kun-Hsien Lee
IPC: H01L29/78 , H01L27/088 , H01L29/165 , H01L29/66 , H01L21/8234 , H01L27/06
Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.
-
公开(公告)号：US20220302118A1
公开(公告)日：2022-09-22
申请号：US17230975
申请日：2021-04-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuo-Hsing Lee , Kun-Hsien Lee , Sheng-Yuan Hsueh , Chang-Chien Wong , Ching-Hsiang Tseng , Tsung-Hsun Wu , Chi-Horn Pai , Shih-Chieh Hsu
IPC: H01L27/108
Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.
-
公开(公告)号：US20190355849A1
公开(公告)日：2019-11-21
申请号：US16529523
申请日：2019-08-01
Applicant: United Microelectronics Corp.
Inventor： LING-CHUN CHOU , Kun-Hsien Lee
IPC: H01L29/78 , H01L29/66 , H01L27/088 , H01L27/06 , H01L21/8234
Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.
-
Patent Agency Ranking
公开(公告)号：US09799770B2
公开(公告)日：2017-10-24
申请号：US15064618
申请日：2016-03-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ting-Yao Lin , Ling-Chun Chou , Kun-Hsien Lee
IPC: H01L29/78 , H01L29/423 , H01L29/08 , H01L29/167 , H01L29/165
CPC classification number: H01L29/7851 , H01L29/0865 , H01L29/0882 , H01L29/165 , H01L29/167 , H01L29/4236 , H01L29/7816 , H01L29/7825 , H01L29/7848
Abstract: The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.
-
公开(公告)号：US20130119479A1
公开(公告)日：2013-05-16
申请号：US13736951
申请日：2013-01-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Han Hung , Tsai-Fu Chen , Shyh-Fann Ting , Cheng-Tung Huang , Kun-Hsien Lee , Ta-Kang Lo , Tzyy-Ming Cheng
IPC: H01L27/092
CPC classification number: H01L27/092 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/7848
Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.
Abstract translation: 在本发明中提供一种晶体管结构。 晶体管结构包括：包括N型阱的衬底，设置在N型阱上的栅极，设置在栅极上的间隔物，位于衬垫下方的衬底中的第一轻掺杂区域，P型源极/漏极 位于栅极两侧的衬底中的覆盖P型源/漏区和第一轻掺杂区的硅帽层和设置在硅帽层上的硅化物层，并且仅覆盖硅的一部分 盖层。
-
公开(公告)号：US20250107114A1
公开(公告)日：2025-03-27
申请号：US18380641
申请日：2023-10-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Pin-Tseng Chen , Ling-Chun Chou , Kun-Hsien Lee
Abstract: The invention provides a metal oxide semiconductor (MOS) capacitor structure, which includes a counter-doping region in the channel region directly below the gate. Between the deep ion well and the counter-doping region is a semiconductor region. The doping concentration of the semiconductor region is lower than that of the deep ion well. The P-type well ion implantation processes in the active region of the device can be omitted, so the production cost is lower, and the dosage of the counter-doping region can be reduced, which improves the time-dependent dielectric collapse (TDDB) issue.
-
公开(公告)号：US11450670B1
公开(公告)日：2022-09-20
申请号：US17230975
申请日：2021-04-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuo-Hsing Lee , Kun-Hsien Lee , Sheng-Yuan Hsueh , Chang-Chien Wong , Ching-Hsiang Tseng , Tsung-Hsun Wu , Chi-Horn Pai , Shih-Chieh Hsu
IPC: H01L27/108
Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.
-
公开(公告)号：US20220271161A1
公开(公告)日：2022-08-25
申请号：US17216642
申请日：2021-03-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ling-Chun Chou , Te-Chi Yen , Yu-Hung Chang , Kun-Hsien Lee , Kai-Lin Lee
Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.
-
-
-
-
-
-
-
-
-
Search Results
26
records
(took 0.016 seconds)
