公开(公告)号：US20250107114A1

公开(公告)日：2025-03-27

申请号：US18380641

申请日：2023-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Tseng Chen ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L29/94 ,  H01L29/06

Abstract: The invention provides a metal oxide semiconductor (MOS) capacitor structure, which includes a counter-doping region in the channel region directly below the gate. Between the deep ion well and the counter-doping region is a semiconductor region. The doping concentration of the semiconductor region is lower than that of the deep ion well. The P-type well ion implantation processes in the active region of the device can be omitted, so the production cost is lower, and the dosage of the counter-doping region can be reduced, which improves the time-dependent dielectric collapse (TDDB) issue.

公开(公告)号：US20220271161A1

公开(公告)日：2022-08-25

申请号：US17216642

申请日：2021-03-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ling-Chun Chou ,  Te-Chi Yen ,  Yu-Hung Chang ,  Kun-Hsien Lee ,  Kai-Lin Lee

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.

公开(公告)号：US20240105839A1

公开(公告)日：2024-03-28

申请号：US18528816

申请日：2023-12-05

Applicant: UNITED MICROELECTRONICS CORP

Inventor： Ling-Chun Chou ,  Yu-Hung Chang ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7823 ,  H01L29/0623

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

公开(公告)号：US11881527B2

公开(公告)日：2024-01-23

申请号：US17472680

申请日：2021-09-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ling-Chun Chou ,  Yu-Hung Chang ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7823 ,  H01L29/0623

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

公开(公告)号：US20230253497A1

公开(公告)日：2023-08-10

申请号：US18135198

申请日：2023-04-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ling-Chun Chou ,  Te-Chi Yen ,  Yu-Hung Chang ,  Kun-Hsien Lee ,  Kai-Lin Lee

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7835 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0653

Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.

公开(公告)号：US20230052714A1

公开(公告)日：2023-02-16

申请号：US17472680

申请日：2021-09-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ling-Chun Chou ,  Yu-Hung Chang ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L29/06

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

公开(公告)号：US09978745B2

公开(公告)日：2018-05-22

申请号：US15289988

申请日：2016-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ti Wang ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L27/082 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/082 ,  H01L27/0207 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0813 ,  H01L29/1008 ,  H01L29/407 ,  H01L29/735

Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.

公开(公告)号：US09799770B2

公开(公告)日：2017-10-24

申请号：US15064618

申请日：2016-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Yao Lin ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/167 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4236 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7848

Abstract: The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.

公开(公告)号：US09590072B1

公开(公告)日：2017-03-07

申请号：US14990806

申请日：2016-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ling-Chun Chou

IPC: H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/66537 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: The present invention provides a method of forming a semiconductor device including following steps. Firstly, a fin shaped structure is formed on a substrate, and a gate structure is formed to be across the fin shaped structure. Next, a dielectric layer is formed on the substrate, covering the gate structure, and a gate electrode of the gate structure is removed, to form a first gate trench. Then, a threshold voltage implantation process and a compensated threshold voltage implantation process are sequentially performed in the first gate trench, to implant compensated two dopants respectively. Following these, a work function layer and a conductive layer are formed to fill the first gate trench.

Abstract translation: 本发明提供一种形成半导体器件的方法，包括以下步骤。 首先，在基板上形成翅片状结构，并且形成栅极结构以跨过鳍状结构。 接下来，在衬底上形成介电层，覆盖栅极结构，去除栅极结构的栅电极，形成第一栅极沟槽。 然后，在第一栅极沟槽中依次执行阈值电压注入工艺和补偿阈值电压注入工艺，分别注入补偿的两个掺杂剂。 接下来，形成工作功能层和导电层以填充第一栅极沟槽。

公开(公告)号：US20150108553A1

公开(公告)日：2015-04-23

申请号：US14583211

申请日：2014-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ling-Chun Chou ,  I-Chang Wang ,  Ching-Wen Hung

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.

Abstract translation: 一种用于半导体器件的制造方法，包括提供至少具有玛瑙结构的基板和形成在栅极结构的侧壁上的第一间隔物，进行离子注入以将掺杂剂注入衬底中，形成具有至少一个碳 所述含碳层与所述第一间隔物接触，并进行热处理以在所述含碳层和所述第一间隔物之间​​形成保护层。