公开(公告)号：US20230335622A1

公开(公告)日：2023-10-19

申请号：US18213903

申请日：2023-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chang Lin ,  Bo-Han Huang ,  Chih-Chung Chen ,  Chun-Hsien Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L29/7851 ,  H01L21/02054 ,  H01L21/02052 ,  H01L29/517

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

公开(公告)号：US20230299166A1

公开(公告)日：2023-09-21

申请号：US18201769

申请日：2023-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66045 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/78696

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

公开(公告)号：US20230261102A1

公开(公告)日：2023-08-17

申请号：US18138145

申请日：2023-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

公开(公告)号：US11670710B2

公开(公告)日：2023-06-06

申请号：US17544867

申请日：2021-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

公开(公告)号：US20230157029A1

公开(公告)日：2023-05-18

申请号：US17548607

申请日：2021-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

公开(公告)号：US11646367B2

公开(公告)日：2023-05-09

申请号：US17544846

申请日：2021-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

公开(公告)号：US20220093782A1

公开(公告)日：2022-03-24

申请号：US17544846

申请日：2021-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai

IPC: H01L29/778 ,  H01L29/66

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.

公开(公告)号：US11227944B2

公开(公告)日：2022-01-18

申请号：US16578407

申请日：2019-09-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai

IPC: H01L29/778 ,  H01L29/66

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.

公开(公告)号：US20190221639A1

公开(公告)日：2019-07-18

申请号：US15870267

申请日：2018-01-12

Applicant: United Microelectronics Corp.

Inventor： Kuan-Hao Tseng ,  Yu-Hsiang Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Chueh-Fei Tai ,  Cheng-Ping Kuo

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/10 ,  H01L21/306 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabrication a nanosheet device includes providing forming a stacked layer on a substrate, having first material layers and second material layers in different materials, alternatingly stacked up. The stacked layer is patterned to a stacked fin. A dummy stack is formed on the stacked fin. An etching back process is performed with the dummy stack with spacers to etch the stacked fin and expose the substrate. Laterally etches the first material layers and the second material layers, to have indent portions. Inner spacers fill the indent portions. A first/second source/drain layer is formed on the substrate at both sides of the dummy stack. Etching process is performed to remove the dummy gate of the dummy stack and the selected one of the first material layers and the second material layers between the inner spacers. Metal layer fills between the spacers and the inner spacers.

公开(公告)号：US10211313B2

公开(公告)日：2019-02-19

申请号：US15678125

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Cheng-Ping Kuo ,  Kuan-Hao Tseng

IPC: H01L29/51 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a first recess; forming ferroelectric (FE) layer in the first recess; forming a compressive layer on the FE layer; performing a thermal treatment process; removing the compressive layer; and forming a work function metal layer in the recess.