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    TERNARY CONTENT ADDRESSABLE MEMORY AND TWO-PORT STATIC RANDOM ACCESS MEMORY
    22.
    发明申请
    TERNARY CONTENT ADDRESSABLE MEMORY AND TWO-PORT STATIC RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20220238158A1

    公开(公告)日：2022-07-28

    申请号：US17179418

    申请日：2021-02-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng ,  Chun-Chieh Chang

    IPC: G11C15/04

    Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

    STATIC RANDOM-ACCESS MEMORY (SRAM) CELL ARRAY
    25.
    发明申请
    STATIC RANDOM-ACCESS MEMORY (SRAM) CELL ARRAY 审中-公开

    公开(公告)号：US20170373073A1

    公开(公告)日：2017-12-28

    申请号：US15686169

    申请日：2017-08-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

    IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

    Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

    Static random access memory unit cell structure and static random access memory unit cell layout structure
    28.
    发明申请
    Static random access memory unit cell structure and static random access memory unit cell layout structure 有权
    静态随机存取单元单元格结构和静态随机存取单元布局结构

    公开(公告)号：US20140241027A1

    公开(公告)日：2014-08-28

    申请号：US13776589

    申请日：2013-02-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  Po-Chao Tsao ,  Shu-Ru Wang ,  Chia-Wei Huang ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Chih-Sen Huang

    IPC: G11C11/412

    CPC classification number: G11C11/412 ,  H01L27/0207 ,  H01L27/1104

    Abstract: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.

    Abstract translation: 公开了一种静态随机存取存储器单元布局结构，其中，槽触点设置在一个有源区上，另一个位于一个有源区上。 还公开了一种静态随机存取存储单元单元结构及其制造方法，其中，在上拉晶体管和下拉晶体管的漏极上设置一个槽触点，并且设置金属零互连 在槽触点和另一个上拉晶体管的栅极线上。 因此，没有垂直和水平的金属零互连，没有两次蚀刻的地方。 可以避免缝合凹陷引起的泄漏接头。

    Layout pattern of static random access memory
    29.
    发明申请
    Layout pattern of static random access memory 有权

    公开(公告)号：US20250095724A1

    公开(公告)日：2025-03-20

    申请号：US18966047

    申请日：2024-12-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Yu-Fang Chen ,  Chun-Yen Tseng ,  Tzu- Feng Chang ,  Chun-Chieh Chang

    IPC: G11C11/412 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

    Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

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