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103 条记录 (耗时 0.029 秒)

    Flexible RAM clock enable
    21.
    发明授权
    Flexible RAM clock enable 失效
    灵活的RAM时钟使能

    公开(公告)号：US07397726B1

    公开(公告)日：2008-07-08

    申请号：US11399771

    申请日：2006-04-07

    申请人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

    发明人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

    IPC分类号： G11C8/00 ,  G11C7/10

    CPC分类号： G11C7/1075 ,  G11C8/18 ,  H03K19/1737

    摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. The first set of configuration logic is also configurable to provide a first port core clock signal for controlling the memory block core. The first port core clock signal can either be the same as the first port input clock signal, or can be controlled independently from the first port input clock signal. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block. The second set of configuration logic is also configurable to provide a second port core clock signal for controlling the memory block core. The second port core clock signal can be controlled independently from the second port input clock signal.

    摘要翻译： 第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。 第一组配置逻辑也可配置为提供用于控制存储块核心的第一端口核心时钟信号。 第一个端口核心时钟信号可以与第一个端口输入时钟信号相同，也可以独立于第一个端口输入时钟信号进行控制。 第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。 第二组配置逻辑也可配置为提供用于控制存储块核心的第二端口核心时钟信号。 可以独立于第二端口输入时钟信号来控制第二端口核心时钟信号。

    Systems and methods for reducing static and total power consumption in programmable logic device architectures
    22.
    发明授权
    Systems and methods for reducing static and total power consumption in programmable logic device architectures 有权
    用于减少可编程逻辑器件架构中的静态和总功耗的系统和方法

    公开(公告)号：US07287171B1

    公开(公告)日：2007-10-23

    申请号：US10796502

    申请日：2004-03-08

    申请人： David Mendel ,  Vaughn Betz

    发明人： David Mendel ,  Vaughn Betz

    IPC分类号： G06F1/00 ,  G06F11/30

    CPC分类号： H03K19/17784 ,  G06F17/5054

    摘要： A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the synthesis, placement, routing, and period following routing of the programmable logic device.

    摘要翻译： 提供了一种用于降低可编程逻辑器件（PLD）中功耗的方法和系统。 在可编程逻辑器件的路由合成，放置，路由和后续周期期间，通过优选地连续考虑功率消耗作为电路设计的一个因素，可以降低功耗。

    Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements
    24.
    发明授权
    Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements 失效
    用于识别与模板匹配并且将功能块组合成更少的可编程电路元件的设计中的功能块的技术

    公开(公告)号：US06957412B1

    公开(公告)日：2005-10-18

    申请号：US10298259

    申请日：2002-11-15

    申请人： Vaughn Betz ,  Elias Ahmed ,  David Neto

    发明人： Vaughn Betz ,  Elias Ahmed ,  David Neto

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： Techniques are provided that combine functional blocks in a user design into fewer programmable circuit elements. Systems and methods of the present invention can combine functional blocks in a user design into a single programmable circuit element. A plurality of functional blocks in a user design that can be combined are identified. The possible combinations of functional blocks can be sorted according to a gain function. The gain function can, for example, weigh routing delays caused by a combination. The most desirable combination is selected from the sorted list of possible combinations. The selected combination is checked to see if it is feasible in light of electrical and user-specified constraints. If the combination is feasible, the combination is performed. Combinations continue to be performed by selecting the most desirable combinations from the sorted list.

    摘要翻译： 提供了将用户设计中的功能块组合成更少的可编程电路元件的技术。 本发明的系统和方法可以将用户设计中的功能块组合成单个可编程电路元件。 识别可以组合的用户设计中的多个功能块。 功能块的可能组合可以根据增益函数进行排序。 增益功能可以例如衡量由组合引起的路由延迟。 最合适的组合是从可能组合的排序列表中选择的。 根据电气和用户指定的限制，检查所选择的组合是否可行。 如果组合可行，则执行组合。 组合继续通过从排序列表中选择最理想的组合来执行。

    Systems and methods for reducing static and total power consumption
    25.
    发明授权
    Systems and methods for reducing static and total power consumption 失效
    降低静态和总功耗的系统和方法

    公开(公告)号：US08156355B2

    公开(公告)日：2012-04-10

    申请号：US12329051

    申请日：2008-12-05

    申请人： David Mendel ,  Vaughn Betz

    发明人： David Mendel ,  Vaughn Betz

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/32

    摘要： A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.

    摘要翻译： 提供了一种用于降低可编程逻辑器件（PLD）中功耗的方法和系统。 在可编程逻辑器件的技术映射，路由和后续周期期间，优选地可以连续地考虑功率消耗作为电路设计中的一个因素来降低功耗。

    Error correction for programmable logic integrated circuits
    26.
    发明授权
    Error correction for programmable logic integrated circuits 有权
    可编程逻辑集成电路的误差校正

    公开(公告)号：US08112678B1

    公开(公告)日：2012-02-07

    申请号：US11955910

    申请日：2007-12-13

    申请人： David Lewis ,  Vaughn Betz

    发明人： David Lewis ,  Vaughn Betz

    IPC分类号： G06F11/00

    CPC分类号： G06F11/106

    摘要： Systems and methods for detecting and correcting errors in programmable logic ICs are provided. In one embodiment, a scrubber periodically reads the memory cells in a programmable logic IC, detects and corrects any errors, and writes the corrected contents back into the memory cell. In another embodiment, regions of memory cells in a programmable logic IC each have associated error correcting circuitry which operates to continuously detect and correct errors as they occur. Error correcting circuitry can further be designed to reduce static hazards. It may be more desirable to design programmable logic IC routing architectures that reduce the number of memory cells needed to implement a given function. Error correcting circuitry can be provided for configuration memory or for an embedded memory block on a programmable logic IC.

    摘要翻译： 提供了用于检测和校正可编程逻辑IC中的错误的系统和方法。 在一个实施例中，洗涤器周期性地读取可编程逻辑IC中的存储器单元，检测和校正任何错误，并将校正的内容写入存储单元。 在另一个实施例中，可编程逻辑IC中的存储器单元的区域各自具有相关联的误差校正电路，其操作以在错误发生时连续地检测和校正错误。 误差校正电路可进一步设计，以减少静电危害。 可能更需要设计可编程逻辑IC路由架构，减少实现给定功能所需的存储器单元的数量。 可以为配置存储器或可编程逻辑IC上的嵌入式存储器块提供纠错电路。

    Power-driven timing analysis and placement for programmable logic
    27.
    发明授权
    Power-driven timing analysis and placement for programmable logic 有权
    用于可编程逻辑的功率驱动时序分析和放置

    公开(公告)号：US08099692B1

    公开(公告)日：2012-01-17

    申请号：US12953764

    申请日：2010-11-24

    申请人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    发明人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  Y02T10/82

    摘要： An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided design flow) will then take these timing considerations into account while performing partitioning of the device. A user's logic design is implemented into the logic array blocks taking into a voltage drop seen at those logic array blocks. Faster paths of the logic design are placed into faster logic array blocks, such as those in a core region of the integrated circuit.

    摘要翻译： 集成电路被分为两个或更多个不同的区域，每个区域是不同的电压域。 在每个区域，电压降及其对性能的影响将被量化。 然后，在执行设备分区时，会考虑到这些时间考虑因素，地方和路线引擎（或计算机辅助设计流程的另一个工具）将考虑这些时间考虑因素。 用户的逻辑设计被实现为在这些逻辑阵列块处看到的电压降的逻辑阵列块中。 将逻辑设计的更快的路径放置在更快的逻辑阵列块中，例如集成电路的核心区域中的那些。

    Techniques for grouping circuit elements into logic blocks
    28.
    发明授权
    Techniques for grouping circuit elements into logic blocks 失效
    将电路元件分组成逻辑块的技术

    公开(公告)号：US07707532B1

    公开(公告)日：2010-04-27

    申请号：US11844216

    申请日：2007-08-23

    申请人： Ketan Padalia ,  Kimberly Bozman ,  Vaughn Betz

    发明人： Ketan Padalia ,  Kimberly Bozman ,  Vaughn Betz

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  Y02T10/82

    摘要： Techniques are provided for grouping circuits in a user design for a programmable integrated circuit into logic blocks. A packing tool separates each circuit element into individual abstract blocks and groups the abstract block into logic blocks. A determination is made whether placement information indicates that a design goal would be improved by rearranging at least a portion of the user design. The user design can be rearranged by moving one or more of the abstract blocks into different logic blocks than the ones they were previously grouped with. Circuit elements in the same logic block can be separated and placed into different logic blocks to improve routability of the user design and signal timing.

    摘要翻译： 提供了用于将可编程集成电路的用户设计中的电路分组成逻辑块的技术。 包装工具将每个电路元件分成单独的抽象块，并将抽象块分组成逻辑块。 确定放置信息是否指示通过重新排列用户设计的至少一部分来提高设计目标。 可以通过将抽象块中的一个或多个移动到与之前分组的逻辑块不同的逻辑块中来重新排列用户设计。 相同逻辑块中的电路元件可以分离并放置到不同的逻辑块中，以改善用户设计和信号时序的可布线性。