公开(公告)号：US6150263A

公开(公告)日：2000-11-21

申请号：US188920

申请日：1998-11-09

Applicant: Kevin Lin ,  Ching-Chiao Hao ,  Kun-Chi Lin

Inventor： Kevin Lin ,  Ching-Chiao Hao ,  Kun-Chi Lin

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76885

Abstract: A method of forming small dimension wires by an isotropic removal process. The method provides a substrate with an insulation layer. A first conductive layer and a second conductive layer are formed on the insulation layer. A wire pattern is formed on a photoresist layer after the coating process and the sequential exposure and development process. Part of the second conductive layer is removed by using the wire pattern on the photoresist layer as a mask, and thus part of the second conductive layer with wires is remained. Isotropic etching the peripheral part of the second conductive layer and thus the part of wire pattern with a smaller dimension is remained. Using the wire pattern with a smaller dimension as a mask to anisotropic etch the first conductive layer until the surface of the insulation layer is exposed, and thus the process of fabricating small dimension is finished.

Abstract translation: 通过各向同性去除方法形成小尺寸线的方法。 该方法提供具有绝缘层的基板。 第一导电层和第二导电层形成在绝缘层上。 在涂布工艺和顺序曝光和显影处理之后，在光致抗蚀剂层上形成线图案。 通过使用光致抗蚀剂层上的线图案作为掩模来去除部分第二导电层，因此残留了具有导线的第二导电层的一部分。 残留了各向同性蚀刻第二导电层的周边部分，因此保留了具有较小尺寸的线图案的部分。 使用较小尺寸的导线图案作为掩模以对第一导电层进行各向异性蚀刻，直到绝缘层的表面露出，从而完成制造小尺寸的工艺。

公开(公告)号：USD419462S

公开(公告)日：2000-01-25

申请号：US101139

申请日：1999-02-24

Applicant: Kevin Lin

Designer： Kevin Lin

公开(公告)号：US20160329438A1

公开(公告)日：2016-11-10

申请号：US15151381

申请日：2016-05-10

Applicant: Chytra Pawashe ,  Kevin Lin ,  Anurag Chaudhry ,  Raseong Kim ,  Seiyon Kim ,  Kelin Kuhn ,  Sasikanth Manipatruni ,  Rafael Rios ,  Ian A. Young

Inventor： Chytra Pawashe ,  Kevin Lin ,  Anurag Chaudhry ,  Raseong Kim ,  Seiyon Kim ,  Kelin Kuhn ,  Sasikanth Manipatruni ,  Rafael Rios ,  Ian A. Young

IPC: H01L29/84 ,  H01H59/00 ,  H01L29/161 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L29/84 ,  B82Y10/00 ,  H01H1/0094 ,  H01H9/0271 ,  H01H59/0009 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161

Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.

Abstract translation: 描述了基于纳米线的机械开关装置。 例如，纳米线继电器包括布置在衬底上方的空隙中的纳米线。 纳米线具有锚固部分和悬挂部分。 第一栅电极邻近空隙设置，并与纳米线隔开。 第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线隔开。

公开(公告)号：US20160104642A1

公开(公告)日：2016-04-14

申请号：US14965734

申请日：2015-12-10

Applicant: Robert L. Bristol ,  Kevin Lin ,  Kanwal Jit Singh ,  Alan M. Myers ,  Richard E. Schenker

Inventor： Robert L. Bristol ,  Kevin Lin ,  Kanwal Jit Singh ,  Alan M. Myers ,  Richard E. Schenker

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.

公开(公告)号：US08610986B2

公开(公告)日：2013-12-17

申请号：US12419210

申请日：2009-04-06

Applicant: Kanti Jain ,  Junghun Chae ,  Kevin Lin ,  Hyunjong Jin

Inventor： Kanti Jain ,  Junghun Chae ,  Kevin Lin ,  Hyunjong Jin

IPC: G02B26/08 ,  G02B26/10 ,  G02B26/12

CPC classification number: G02B26/0833 ,  G02B5/0833 ,  G02B5/0858 ,  G03F7/70291

Abstract: Micromirrors and micromirror arrays described herein are useful, for example in maskless photolithography systems and methods and projection display devices and methods. According to one aspect, the micromirrors comprise a polymer structural layer and a reflective dielectric multilayer for selective reflection and/or redirection of incoming electromagnetic radiation. According to another aspect, incorporation of a reflective dielectric multilayer allows for use of polymer structural materials in micromirrors and prevents damage to such polymer materials due to excessive heating from absorption of electromagnetic radiation, as the reflective dielectric multilayers are highly reflective and minimize heating of the micromirror components. According to yet a further aspect, top down fabrication methods are described herein for making a micromirror comprising a polymer structural layer and a reflective dielectric multilayer.

Abstract translation: 本文所述的微镜和微镜阵列是有用的，例如在无掩模光刻系统和方法以及投影显示装置和方法中。 根据一个方面，微镜包括用于选择性反射和/或重定向输入电磁辐射的聚合物结构层和反射电介质多层。 根据另一方面，引入反射电介质多层允许在微反射镜中使用聚合物结构材料，并且防止由于电磁辐射的吸收导致的过度加热而损坏这种聚合物材料，因为反射电介质多层是高度反射性的并且最小化 微镜组件。 根据又一方面，本文描述了自顶向下的制造方法，用于制造包括聚合物结构层和反射电介质多层的微镜。

公开(公告)号：US20100255426A1

公开(公告)日：2010-10-07

申请号：US12419210

申请日：2009-04-06

Applicant: Kanti JAIN ,  Junghun Chae ,  Kevin Lin ,  Hyunjong Jin

Inventor： Kanti JAIN ,  Junghun Chae ,  Kevin Lin ,  Hyunjong Jin

IPC: G03F7/20 ,  B32B37/02 ,  G02B5/08 ,  G02B1/10 ,  G02B26/00 ,  G02B26/02

CPC classification number: G02B26/0833 ,  G02B5/0833 ,  G02B5/0858 ,  G03F7/70291

Abstract: Micromirrors and micromirror arrays described herein are useful, for example in maskless photolithography systems and methods and projection display devices and methods. According to one aspect, the micromirrors comprise a polymer structural layer and a reflective dielectric multilayer for selective reflection and/or redirection of incoming electromagnetic radiation. According to another aspect, incorporation of a reflective dielectric multilayer allows for use of polymer structural materials in micromirrors and prevents damage to such polymer materials due to excessive heating from absorption of electromagnetic radiation, as the reflective dielectric multilayers are highly reflective and minimize heating of the micromirror components. According to yet a further aspect, top down fabrication methods are described herein for making a micromirror comprising a polymer structural layer and a reflective dielectric multilayer.

Abstract translation: 本文所述的微镜和微镜阵列是有用的，例如在无掩模光刻系统和方法以及投影显示装置和方法中。 根据一个方面，微镜包括用于选择性反射和/或重定向输入电磁辐射的聚合物结构层和反射电介质多层。 根据另一方面，引入反射电介质多层允许在微反射镜中使用聚合物结构材料，并且防止由于电磁辐射的吸收导致的过度加热而损坏这种聚合物材料，因为反射电介质多层是高度反射性的并且使得 微镜组件。 根据又一方面，本文描述了自顶向下的制造方法，用于制造包括聚合物结构层和反射电介质多层的微镜。

公开(公告)号：US20100143848A1

公开(公告)日：2010-06-10

申请号：US12331131

申请日：2008-12-09

Applicant: Kanti Jain ,  Kevin Lin

Inventor： Kanti Jain ,  Kevin Lin

IPC: G03F7/20

CPC classification number: H05K1/0283 ,  B23K26/40 ,  B23K2103/172 ,  B81B2201/0292 ,  B81B2203/0109 ,  B81B2207/07 ,  B81C1/0019 ,  H05K3/0032 ,  H05K3/007 ,  H05K2201/09109 ,  H05K2203/0554 ,  H05K2203/308

Abstract: Described herein are processing techniques for fabrication of stretchable and/or flexible electronic devices using laser ablation patterning methods. The laser ablation patterning methods utilized herein allow for efficient manufacture of large area (e.g., up to 1 mm2 or greater or 1 m2 or greater) stretchable and/or flexible electronic devices, for example manufacturing methods permitting a reduced number of steps. The techniques described herein further provide for improved heterogeneous integration of components within an electronic device, for example components having improved alignment and/or relative positioning within an electronic device. Also described herein are flexible and/or stretchable electronic devices, such as interconnects, sensors and actuators.

Abstract translation: 这里描述了使用激光烧蚀图案化方法制造可拉伸和/或柔性电子器件的处理技术。 本文使用的激光烧蚀图案化方法允许有效地制造大面积（例如，高达1mm 2或更大或1m 2或更大）的可拉伸和/或柔性电子器件，例如允许减少步数的制造方法。 本文描述的技术进一步提供了改进的电子设备内的组件的异构集成，例如具有电子设备内的改进的对准和/或相对定位的组件。 本文还描述了柔性和/或可拉伸的电子设备，例如互连，传感器和致动器。

公开(公告)号：USD556873S1

公开(公告)日：2007-12-04

申请号：US29248556

申请日：2006-08-22

Applicant: Kevin Lin ,  Camel Hou ,  Lisa Zou

Designer： Kevin Lin ,  Camel Hou ,  Lisa Zou

公开(公告)号：USD545413S1

公开(公告)日：2007-06-26

申请号：US29248463

申请日：2006-08-17

Applicant: Kevin Lin ,  Lisa Zou

Designer： Kevin Lin ,  Lisa Zou

公开(公告)号：US07111386B2

公开(公告)日：2006-09-26

申请号：US11266418

申请日：2005-11-03

Applicant: Chao-Peng Chen ,  Kevin Lin ,  Jei-Wei Chang ,  Kochan Ju ,  Hui-Chuan Wang

Inventor： Chao-Peng Chen ,  Kevin Lin ,  Jei-Wei Chang ,  Kochan Ju ,  Hui-Chuan Wang

IPC: G11B5/127 ,  H04R31/00

CPC classification number: B82Y10/00 ,  G11B5/3116 ,  G11B5/3163 ,  G11B5/3903 ,  Y10T29/49021 ,  Y10T29/49032 ,  Y10T29/49041 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052 ,  Y10T29/49128

Abstract: A major problem in Lead Overlay design for GMR structures is that the magnetic read track width is wider than the physical read track width. This is due to high interfacial resistance between the leads and the GMR layer which is an unavoidable side effect of prior art methods. The present invention uses electroplating preceded by a wet etch to fabricate the leads. This approach requires only a thin protection layer over the GMR layer to ensure that interface resistance is minimal. Using wet surface cleaning avoids sputtering defects and plating is compatible with this so the cleaned surface is preserved Only a single lithography step is needed to define the track since there is no re-deposition involved.