公开(公告)号：US20070124101A1

公开(公告)日：2007-05-31

申请号：US11289088

申请日：2005-11-29

申请人： Maximino Aguilar ,  Charles Johns ,  Mark Nutter ,  James Stafford

发明人： Maximino Aguilar ,  Charles Johns ,  Mark Nutter ,  James Stafford

IPC分类号： G01K1/00

CPC分类号： G06F1/206 ,  G01K3/005 ,  G01K7/015

摘要： A computer implemented method, data processing system, computer usable code, and apparatus are provided for generation of software thermal profiles for applications executing on a set of processors. Sampling is performed of the hardware operations occurring in a set of processors during the execution of a set of workloads to create sampled information. A thermal index is then generated based on the sampled information.

摘要翻译： 提供计算机实现的方法，数据处理系统，计算机可用代码和装置，用于生成用于在一组处理器上执行的应用的软件热分布。 在一组工作负载的执行期间执行在一组处理器中发生的硬件操作的采样以创建采样信息。 然后基于采样信息产生热指数。

公开(公告)号：US20070124100A1

公开(公告)日：2007-05-31

申请号：US11289066

申请日：2005-11-29

申请人： Maximino Aguilar ,  Charles Johns ,  Mark Nutter ,  James Stafford

发明人： Maximino Aguilar ,  Charles Johns ,  Mark Nutter ,  James Stafford

IPC分类号： G01K1/00 ,  G01K3/00

CPC分类号： G01K7/425 ,  G01K1/022 ,  G06F1/206 ,  G06F9/4893 ,  Y02D10/24

摘要： A computer implemented method, data processing system, and computer usable code are provided for generation of hardware thermal profiles for a set of processors. Sampling is performed of the thermal states of the set of processors during the execution of a set of workloads to create sampled information. The sampled information and thermal characteristics of the set of processors are combined and a thermal index is generated based on the sampled information and characteristics of the set of processors.

摘要翻译： 提供计算机实现的方法，数据处理系统和计算机可用代码，用于生成用于一组处理器的硬件热分布。 在一组工作负载的执行期间执行处理器集合的热状态的采样以创建采样信息。 组合处理器的采样信息和热特性被组合，并且基于采样的信息和该组处理器的特性来生成热指数。

公开(公告)号：US20070113044A1

公开(公告)日：2007-05-17

申请号：US11621315

申请日：2007-01-09

申请人： Michael Day ,  Jonathan DeMent ,  Charles Johns

发明人： Michael Day ,  Jonathan DeMent ,  Charles Johns

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F2212/654 ,  G06F2212/684

摘要： A method and an apparatus are provided for efficiently managing the operation of a translation buffer. A software and hardware apparatus and method are utilized to pre-load a translation buffer to prevent poor operation as a result of slow warming of a cache. A software pre-load mechanism may be provided for preloading a translation lookaside buffer (TLB) via a hardware implemented controller. Following preloading of the TLB, control of accessing the TLB may be handed over to the hardware implemented controller. Upon an application context switch operation, the software preload mechanism may be utilized again to preload the TLB with new translation information for the newly active application instance.

摘要翻译： 提供了一种用于有效地管理翻译缓冲器的操作的方法和装置。 使用软件和硬件装置和方法来预加载翻译缓冲器，以防止由于缓存缓慢升温而造成的不良操作。 可以提供软件预加载机制，用于经由硬件实现的控制器来预加载翻译后备缓冲器（TLB）。 在TLB的预加载之后，可以将访问TLB的控制权交给硬件实现的控制器。 在应用程序上下文切换操作时，可以再次利用软件预载机制来为新活动的应用实例的新的翻译信息预加载TLB。

公开(公告)号：US20070106428A1

公开(公告)日：2007-05-10

申请号：US11271460

申请日：2005-11-10

申请人： Takashi Omizo ,  Charles Johns ,  Michael Wang ,  Kazuaki Yazawa ,  Toshiyuki Hiroi

发明人： Takashi Omizo ,  Charles Johns ,  Michael Wang ,  Kazuaki Yazawa ,  Toshiyuki Hiroi

IPC分类号： G05D23/00

CPC分类号： G05D23/19

摘要： Systems and methods for sensing temperatures of multiple functional blocks within a digital device and controlling the operation of these functional blocks in a manner that selectively reduces temperatures associated with some of the functional blocks, but not others. One embodiment comprises an integrated circuit having multiple functional blocks (such as processor cores) and a set of thermal sensors coupled to sense the temperatures of the functional blocks. The integrated circuit includes control circuitry configured to receive signals from the thermal sensors, detect thermal events in the functional blocks and to individually adjust operation of the functional blocks to reduce the temperatures causing the thermal events. In one embodiment, the control circuitry includes a detection/control circuit coupled to each of the functional blocks and a thermal management unit configured to evaluate detected thermal events and to determine actions to be taken in response to the thermal events.

摘要翻译： 用于感测数字设备内的多个功能块的温度的系统和方法，并且以选择性地降低与一些功能块相关联的温度而不是其它功能块的方式来控制这些功能块的操作。 一个实施例包括具有多个功能块（例如处理器核）的集成电路和耦合以感测功能块的温度的一组热传感器。 集成电路包括控制电路，其被配置为从热传感器接收信号，检测功能块中的热事件并且单独地调整功能块的操作以降低导致热事件的温度。 在一个实施例中，控制电路包括耦合到每个功能块的检测/控制电路和被配置为评估检测到的热事件并且确定响应于热事件而采取的动作的热管理单元。

公开(公告)号：US20070079018A1

公开(公告)日：2007-04-05

申请号：US11207986

申请日：2005-08-19

申请人： Michael Day ,  Charles Johns ,  Peichun Liu ,  Todd Swanson ,  Thuong Truong

发明人： Michael Day ,  Charles Johns ,  Peichun Liu ,  Todd Swanson ,  Thuong Truong

IPC分类号： G06F13/00

CPC分类号： G06F13/32 ,  G06F13/1642

摘要： A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

摘要翻译： 提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。 系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。

公开(公告)号：US20070043936A1

公开(公告)日：2007-02-22

申请号：US11207971

申请日：2005-08-19

申请人： Michael Day ,  Charles Johns ,  John Liberty ,  Todd Swanson

发明人： Michael Day ,  Charles Johns ,  John Liberty ,  Todd Swanson

IPC分类号： G06F7/38

CPC分类号： G06F13/24

摘要： A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

摘要翻译： 提供了一种用于与处理器事件设施进行通信的系统和方法。 系统和方法利用通道接口作为与处理器事件设施通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。

公开(公告)号：US20060253661A1

公开(公告)日：2006-11-09

申请号：US11120909

申请日：2005-05-03

申请人： Brian Bass ,  Thomas Jeremiah ,  Charles Johns ,  David Shippy ,  Thuong Truong

发明人： Brian Bass ,  Thomas Jeremiah ,  Charles Johns ,  David Shippy ,  Thuong Truong

IPC分类号： G06F13/00 ,  G06F12/06

CPC分类号： G06F12/06

摘要： The present invention utilizes the good qualities of a single address concentrator (AC), without any extra chips or wires, and distributes the AC function among the various chips, making use of the fact that each chip in the system has a copy of the AC function therein. Using the distributed address concentrator function, each chip will handle approximately one-fourth of the command traffic and the average latency of servicing the commands will be approximately the same across each chip in the system.

公开(公告)号：US20060026309A1

公开(公告)日：2006-02-02

申请号：US10902474

申请日：2004-07-29

申请人： Michael Day ,  Charles Johns ,  Peichun Liu ,  Thuong Truong ,  Takeshi Yamazaki

发明人： Michael Day ,  Charles Johns ,  Peichun Liu ,  Thuong Truong ,  Takeshi Yamazaki

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

摘要翻译： 本发明提供了一种用于在直接存储器访问（DMA）设备中创建存储障碍的方法和装置。 接收到存储器屏障命令并接收存储器命令。 内存命令是根据内存屏障命令执行的。 基于内存障碍命令启动总线操作。 基于总线操作接收总线操作确认。 基于总线操作确认执行存储器障碍命令。 在特定方面，存储器屏障命令是直接存储器访问同步（dmasync），并且直接存储器访问强制执行输入/输出（dmaeie））命令的按顺序执行。

公开(公告)号：US20050055507A1

公开(公告)日：2005-03-10

申请号：US10655367

申请日：2003-09-04

申请人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

发明人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

IPC分类号： G06F12/00 ,  G06F12/12

CPC分类号： G06F12/126

摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

摘要翻译： 本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。 根据地址未命中创建类标识符。 替换管理表可用于读取类标识符以创建标签替换控制标记。 包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

公开(公告)号：US07290106B2

公开(公告)日：2007-10-30

申请号：US10976260

申请日：2004-10-28

申请人： Michael Norman Day ,  Charles Johns ,  Thuong Truong

发明人： Michael Norman Day ,  Charles Johns ,  Thuong Truong

IPC分类号： G06F12/00

CPC分类号： G06F12/126 ,  G06F12/0848 ,  G06F2212/2515

摘要： The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.

摘要翻译： 本发明提供了一种用于处理器将数据写入高速缓存或其他快速存储器的方法，而不将其写入主存储器。 此外，数据被“锁定”到高速缓存或其他快速存储器中，直到它被加载使用为止。 数据保留在锁定缓存中，直到它在软件控制下被特别覆盖为止。 锁定缓存或其他快速存储器可用作附加系统内存。 在本发明的实施例中，锁定高速缓存是多组关联高速缓存的一组或多组方式，但不是所有的集合或方式。