公开(公告)号：US20230078017A1

公开(公告)日：2023-03-16

申请号：US17477004

申请日：2021-09-16

Applicant: Wolfspeed, Inc.

Inventor： Evan Jones ,  Saptha Sriram ,  Kyle Bothe

IPC: H01L29/10 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812

Abstract: A semiconductor device includes a substrate having an upper surface including a recess region, a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact, a drain contact, and a source contact on the semiconductor structure. The recess region does not vertically overlap the drain contact or the source contact.

公开(公告)号：US20220302291A1

公开(公告)日：2022-09-22

申请号：US17834013

申请日：2022-06-07

Applicant: Wolfspeed, Inc.

Inventor： Jia Guo ,  Kyle Bothe ,  Scott Sheppard

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/40

Abstract: A transistor device according to some embodiments includes a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The device includes an interlayer dielectric layer on the surface dielectric layer that extends over the gate and into the aperture in the surface dielectric layer, and a multiple-stepped field plate on the interlayer dielectric layer. The multiple-stepped field plate is laterally spaced apart from the gate. A recessed portion of the multiple-stepped field plate is above the aperture in the surface dielectric layer, and the multiple-stepped field plate includes a first step adjacent the recessed portion of the field plate on a side of the field plate opposite the gate, and a second step adjacent the first step.

公开(公告)号：US20220130966A1

公开(公告)日：2022-04-28

申请号：US17081476

申请日：2020-10-27

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Jia Guo ,  Terry Alcorn ,  Fabian Radulescu ,  Scott Sheppard

IPC: H01L29/40 ,  H01L29/417

Abstract: A transistor device includes a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The transistor device includes an interlayer dielectric layer on the surface dielectric layer, and a field plate on the interlayer dielectric layer. The field plate is laterally spaced apart from the gate, and at least a portion of the field plate includes a recessed portion above the aperture in the surface dielectric layer.

公开(公告)号：US12224318B2

公开(公告)日：2025-02-11

申请号：US17669479

申请日：2022-02-11

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Chloe Hawes ,  Jennifer Gao ,  Scott Sheppard

IPC: H01L29/08 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/778

Abstract: A HEMT transistor has a semiconductor layer structure that comprises a Group III nitride-based channel layer and a higher bandgap Group III nitride-based barrier layer on the channel layer. A gate finger and first and second source/drain contacts are provided on the semiconductor layer structure. A first source/drain region is provided in the semiconductor layer structure that includes a first implanted region that is underneath the first source/drain contact and a first auxiliary implanted region. A depth of the first implanted region is at least twice a depth of the first auxiliary implanted a region. The first source/drain region extends inwardly a first distance from a lower edge of an inner sidewall of the first source/drain contact, and extends outwardly a second smaller distance from a lower edge of an outer sidewall of the first source/drain contact.

公开(公告)号：US20240429230A1

公开(公告)日：2024-12-26

申请号：US18337657

申请日：2023-06-20

Applicant: Wolfspeed, Inc.

Inventor： Matthew King ,  Chris Hardiman ,  Kyle Bothe ,  Jeremy Fisher

IPC: H01L27/06 ,  H01L21/8252 ,  H01L23/66 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor device includes a semiconductor structure comprising first and second semiconductor layers having different bandgaps, first and second contacts on the semiconductor structure and free of a gate structure therebetween, and a resistor comprising a portion of the semiconductor structure that electrically connects the first and second contacts. The portion of the semiconductor structure may be a second portion of the second semiconductor layer that is recessed in thickness relative to a first portion thereof, and/or may include a passivation layer in direct contact with the second semiconductor layer. Related devices, packages, and fabrication methods are discussed.

公开(公告)号：US20240421193A1

公开(公告)日：2024-12-19

申请号：US18333632

申请日：2023-06-13

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Jia Guo ,  Christer Hallin ,  Alexander V. Suvorov ,  Chris Hardiman ,  Scott Sheppard

IPC: H01L29/20 ,  H01L29/205 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778

Abstract: Semiconductor devices with reduced contact resistance of ohmic contacts are provided. In one example, the semiconductor device includes a Group III-nitride semiconductor structure. The Group III-nitride semiconductor structure includes a channel layer and a barrier layer on the channel layer. The semiconductor device includes an implanted region extending into the channel layer. The implanted region includes a distribution of implanted dopants. The semiconductor device includes a recess in the implanted region. The recess extends through the barrier layer into the channel layer. The semiconductor device includes an ohmic contact within the recess.

公开(公告)号：US20240290876A1

公开(公告)日：2024-08-29

申请号：US18173534

申请日：2023-02-23

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Chris Hardiman ,  Scott Sheppard

IPC: H01L29/778 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66462

Abstract: Semiconductor device having nitrogen-polar (N-polar) Group III-nitride structures are provided. In one example, a semiconductor device may include an N-polar Group III-nitride semiconductor structure. The N-polar Group III-nitride semiconductor structure may have a first region and a second region. The N-polar Group III-nitride semiconductor structure may have a first surface and a second surface opposing the first surface. The second surface may be a planar surface. The semiconductor device may include an isolation implant region extending from the second surface into the N-polar Group III-nitride semiconductor structure to a depth sufficient to provide electrical isolation between the first region and the second region of the N-polar Group III-nitride semiconductor structure.

公开(公告)号：US12015075B2

公开(公告)日：2024-06-18

申请号：US17325628

申请日：2021-05-20

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Joshua Bisges

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324 ,  H01L21/76 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/30612 ,  H01L21/7605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/7786 ,  H01L21/02252 ,  H01L21/26546 ,  H01L21/3245

Abstract: A method of forming a high electron mobility transistor (HEMT) includes: providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 Ω/sq.

公开(公告)号：US20240072732A1

公开(公告)日：2024-02-29

申请号：US17900652

申请日：2022-08-31

Applicant: Wolfspeed, Inc.

Inventor： Donald Farrell ,  Dan Namishia ,  Kyle Bothe ,  Brad Millon

IPC: H03F1/02 ,  H01L23/66 ,  H03F1/56 ,  H03F3/195

CPC classification number: H03F1/0288 ,  H01L23/66 ,  H03F1/565 ,  H03F3/195 ,  H01L2223/6611 ,  H01L2223/6655 ,  H03F2200/451

Abstract: A transistor die includes a transistor including a control terminal, an output terminal, and a first partial matching circuit. The first partial matching circuit is connected to at least one of the control terminal of the transistor and the output terminal of the transistor, and is configured to tune an input impedance of the transistor die. A packaged device is also provided.

公开(公告)号：US20230395695A1

公开(公告)日：2023-12-07

申请号：US18310684

申请日：2023-05-02

Applicant: Wolfspeed, Inc.

Inventor： Chris Hardiman ,  Matthew King ,  Kyle Bothe

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L29/40 ,  H01L21/3065 ,  H01J37/32

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/407 ,  H01L21/3065 ,  H01J37/321 ,  H01J2237/334

Abstract: A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer, source and drain contacts on the semiconductor structure, and a conductive element in a recess in the barrier layer between the source and drain contacts. The barrier layer has a first thickness adjacent the source or drain contact, a second thickness at a floor of the recess between the conductive element and the channel layer, and the first thickness is about 1.2 times to 4 times greater than the second thickness. Related methods of fabrication using a looped recess process are also discussed.