公开(公告)号：US20240014161A1

公开(公告)日：2024-01-11

申请号：US18369115

申请日：2023-09-15

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Kenneth MA ,  Balakrishna JAYADEV ,  Sagheer AHMAD

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L25/0657 ,  H01L23/5384 ,  H01L2224/16225 ,  H01L2924/1434 ,  H01L2225/0651

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

公开(公告)号：US20230376248A1

公开(公告)日：2023-11-23

申请号：US18226193

申请日：2023-07-25

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Ian A. SWARBRICK ,  Sagheer AHMAD

IPC: G06F3/06 ,  G06F13/40 ,  G06F1/28 ,  G06F1/3287

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0634 ,  G06F13/4022 ,  G06F1/28 ,  G06F3/0679 ,  G06F1/3287 ,  G06F2213/0038

Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

公开(公告)号：US20230290189A1

公开(公告)日：2023-09-14

申请号：US17691896

申请日：2022-03-10

Applicant: XILINX, INC.

Inventor： Yanran CHEN ,  Sagheer AHMAD ,  Amitava MAJUMDAR ,  Pramod BHARDWAJ

IPC: G07C5/00 ,  G06F11/10 ,  H04W4/48

CPC classification number: G07C5/008 ,  G06F11/1004 ,  H04W4/48

Abstract: Embodiments herein describe wrapping non-safety compliant hardware resources with error detection checking to satisfy a safety standard. Doing so permits non-safety compliant hardware to be used to perform one or more tasks in a system that, as a whole, satisfies a particular safety standard (e.g., one of the ASIL QM, A, B, C, and D grades).

公开(公告)号：US20230066736A1

公开(公告)日：2023-03-02

申请号：US17464642

申请日：2021-09-01

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Sagheer AHMAD ,  Ygal ARBEL

IPC: G06F13/42 ,  G06F13/40

Abstract: Embodiments herein describe on-demand packetization where data that is too large to be converted directly into data words (DWs) for a chip-to-chip (C2C) interface are packetized instead. When identifying a protocol word that is larger than the DW of the C2C interface, a protocol layer can perform packetization where a plurality of protocol words are packetized and sent as a transfer. In one embodiment, the protocol layer removes some or all of the control data or signals in the protocol words so that the protocol words no longer exceed the size of the DW. These shortened protocol words can then be mapped to DWs and transmitted as separate packets on the C2C. The protocol layer can then collect the portion of the control data that was removed from the protocol words and transmit this data as a separate packet on the C2C interface.