公开(公告)号：US07126376B2

公开(公告)日：2006-10-24

申请号：US10485374

申请日：2003-05-30

申请人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

发明人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

IPC分类号： H03K19/173 ,  H03K3/037

CPC分类号： G09G3/20 ,  G09G3/3648 ,  G09G5/18 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2310/08

摘要： When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.

摘要翻译： 当通过使用具有大的元件特性变化的晶体管形成缓冲器时，可能会发生输入时钟脉冲与复位脉冲之间的定时偏差。 当定时的偏差变大时，会发生故障，相对于元件特性的变化，操作余量变小。 在形成在绝缘基板上并具有两个TFF（12,13）的定时产生电路中，用于产生点时钟DCK和频率与输入外部的主时钟MCK同步的频率不同的水平时钟HCK 在相对于两个TFF（12,13）的脉冲发生电路15处产生分离的复位脉冲drst和hrst，并且在单独的定时执行复位操作。 因此，即使当通过使用具有大的元件特性变化的TFT和粗略的处理规则形成每个电路时，也可以确保大的操作余量。

公开(公告)号：US20060012557A1

公开(公告)日：2006-01-19

申请号：US11207352

申请日：2005-08-19

申请人： Yoshiharu Nakajima ,  Yoshitoshi Kida ,  Hiroaki Ichikawa

发明人： Yoshiharu Nakajima ,  Yoshitoshi Kida ,  Hiroaki Ichikawa

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G02F1/13394 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2330/021

摘要： When a data processing circuit is formed on an insulating substrate by using TFTs, it is difficult to process a data signal having a high data rate, such as digital display data, at a high speed. In a data processing circuit formed on an insulating substrate by using TFTs, a data signal having a small voltage amplitude input in series is increased in level to a data signal having a large voltage amplitude by a level shift circuit (11), the serial data signal having the large voltage amplitude is converted to parallel data signals by a serial-parallel conversion circuit (12), and then, the parallel data signals are reduced in level to data signals having a small voltage amplitude by level shift circuits (13A and 13B). Therefore, high-speed processing can be applied to digital data signals at a low power consumption.

摘要翻译： 当通过使用TFT在绝缘基板上形成数据处理电路时，难以高速处理诸如数字显示数据的数据速率高的数据信号。 在通过使用TFT形成在绝缘基板上的数据处理电路中，串联输入的电压振幅小的数据信号通过电平移位电路（11）增加到电压振幅较大的数据信号，串行数据 具有大电压幅度的信号通过串行 - 并行转换电路（12）被转换为并行数据信号，然后并行数据信号通过电平移位电路（13A和 13 B）。 因此，可以以低功耗将高速处理应用于数字数据信号。

公开(公告)号：US20050024313A1

公开(公告)日：2005-02-03

申请号：US10485293

申请日：2003-05-28

申请人： Yoshiharu Nakajima ,  Yoshitoshi Kida ,  Hiroaki Ichikawa

发明人： Yoshiharu Nakajima ,  Yoshitoshi Kida ,  Hiroaki Ichikawa

IPC分类号： G02F1/1343 ,  G02F1/133 ,  G02F1/1339 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G02F1/13394 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2330/021

摘要： When a data processing circuit is formed on an insulating substrate by using TFTs, it is difficult to process a data signal having a high data rate, such as digital display data, at a high speed. In a data processing circuit formed on an insulating substrate by using TFTs, a data signal having a small voltage amplitude input in series is increased in level to a data signal having a large voltage amplitude by a level shift circuit (11), the serial data signal having the large voltage amplitude is converted to parallel data signals by a serial-parallel conversion circuit (12), and then, the parallel data signals are reduced in level to data signals having a small voltage amplitude by level shift circuits (13A and 13B). Therefore, high-speed processing can be applied to digital data signals at a low power consumption.

摘要翻译： 当通过使用TFT在绝缘基板上形成数据处理电路时，难以高速处理诸如数字显示数据的数据速率高的数据信号。 在通过使用TFT形成在绝缘基板上的数据处理电路中，串联输入的电压振幅小的数据信号通过电平移位电路（11）增加到电压振幅较大的数据信号，串行数据 具有大电压幅度的信号通过串并转换电路（12）被转换为并行数据信号，然后并行数据信号被电平移位电路（13A和13B）降低到电压振幅较小的数据信号 ）。 因此，可以以低功耗将高速处理应用于数字数据信号。

公开(公告)号：US06459395B1

公开(公告)日：2002-10-01

申请号：US09697726

申请日：2000-10-27

申请人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

发明人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

IPC分类号： H03M166

CPC分类号： G09G3/3696 ,  G09G3/3655 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/027 ,  H03M1/765

摘要： In a reference-voltage-selection-type D/A converter, the channel widths of transistors of MOS switches of gradation selecting units are weighted depending on the selected gradation. Specifically, the channel width of the MOS switches Qn11, Qn12 is represented by W0, the channel width of the MOS switches Qn13, Qp11 is represented by W1, the channel width of the MOS switches Qp12, Qn14 is represented by W2, and the channel width of the MOS switches Qp13, Qp14 is represented by W3. The channel width W3 is set to a size corresponding to the maximum capacitance of a column line, and the other channel widths W0, W1, W2 are set to satisfy the relationship: W0

摘要翻译： 在参考电压选择型D / A转换器中，灰度选择单元的MOS开关的晶体管的沟道宽度根据所选择的灰度进行加权。 具体地，MOS开关Qn11，Qn12的沟道宽度由W0表示，MOS开关Qn13，Qp11的沟道宽度由W1表示，MOS开关Qp12，Qn14的沟道宽度由W2表示，沟道 MOS开关Qp13，Qp14的宽度由W3表示。 通道宽度W3被设置为与列线的最大电容相对应的尺寸，并且另一个通道宽度W0，W1，W2被设置为满足关系：W0

公开(公告)号：US08339387B2

公开(公告)日：2012-12-25

申请号：US11886658

申请日：2007-01-19

申请人： Masaki Murase ,  Daisuke Ito ,  Masaaki Tonogai ,  Yoshitoshi Kida ,  Yoshiharu Nakajima

发明人： Masaki Murase ,  Daisuke Ito ,  Masaaki Tonogai ,  Yoshitoshi Kida ,  Yoshiharu Nakajima

IPC分类号： G09G5/00

CPC分类号： G09G3/3688 ,  G09G3/2096 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0289 ,  G09G2310/08

摘要： A display device able to amplify the same input as a power supply voltage of IC by using low temperature polysilicon having high threshold voltage and large variation and an electronic apparatus using the same, including MCK use level shifters 171-1 and 171-2 of a type where a reset operation is periodically necessary, a logic circuit 173 for using a level shift horizontal synchronization signal Hsync to input reset pulses for the MCK level shifters 171-1 and 171-2 having a period of N horizontal periods shifted in phase by M horizontal periods (note, M

摘要翻译： 一种显示装置，其能够通过使用具有高阈值电压和大变化的低温多晶硅以及使用其的电子装置来放大与IC的电源电压相同的输入电压，包括MCK使用电平移位器171-1和171-2 一种周期性地需要复位操作的类型的逻辑电路173，用于使用电平移位水平同步信号Hsync输入具有N个水平周期的相位偏移的周期的MCK电平移位器171-1和171-2的复位脉冲的逻辑电路173 M个水平周期（注意，M

公开(公告)号：US08018415B2

公开(公告)日：2011-09-13

申请号：US11979481

申请日：2007-11-05

申请人： Hirotoshi Koyama ,  Yoshiharu Nakajima ,  Yoshitoshi Kida ,  Daisuke Ito

发明人： Hirotoshi Koyama ,  Yoshiharu Nakajima ,  Yoshitoshi Kida ,  Daisuke Ito

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3614 ,  G09G3/3655 ,  G09G2300/0876 ,  G09G2310/08

摘要： A display device includes a display unit in which pixels are arranged in a matrix state and a drive circuit selecting respective pixels in the display unit by each row and giving additional potential to pixel electrodes of the pixels by using coupling, in which the drive circuit has a function of allowing the reverse polarity of potential added to pixel electrodes to be a potential which can add suitable voltage to additional potential lines in a frame before adding the additional potential.

摘要翻译： 显示装置包括显示单元，其中像素以矩阵状态布置，驱动电路通过每行选择显示单元中的各个像素，并通过使用耦合向像素的像素电极提供附加电位，其中驱动电路具有 允许添加到像素电极的电位的相反极性的一个功能是在添加附加电位之前可以向帧中的附加电位线添加合适的电压的电位。

公开(公告)号：US07932901B2

公开(公告)日：2011-04-26

申请号：US11880699

申请日：2007-07-24

申请人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

发明人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

IPC分类号： G09G5/00

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2330/021 ,  Y02D10/126

摘要： A timing generating circuit with low power consumption and a small layout area, a display apparatus including the timing generating circuit as one peripheral driving circuit, and a portable terminal including the display apparatus as a display output section are provided. In the timing generating circuit, which is formed on an insulating substrate and generates output pulses SRFF1out to SRFFnout having different frequencies based on a master clock MCK, a clock generating circuit (11) generates an operating clock having a lower frequency than the master clock MCK frequency. Then, a counter section (12) operates based on this operating clock and successively outputs shifted pulses S/R1out to S/Rmount from shift registers (121-1) to (121-m). An output pulse generating section (13) generates output pulses SF1out to SFnout based on combinations of the shifted pulses S/R1out to S/Rmount.

摘要翻译： 具有低功耗和小布局区域的定时发生电路，包括作为一个外围驱动电路的定时发生电路的显示装置和包括作为显示输出部分的显示装置的便携式终端。 在形成在绝缘基板上的定时发生电路中，基于主时钟MCK产生具有不同频率的输出脉冲SRFF1out〜SRFFnout，时钟发生电路（11）生成频率低于主时钟MCK的工作时钟 频率。 然后，基于该工作时钟，计数部（12）工作，从移位寄存器（121-1）至（121-m）依次输出移位脉冲S / R1out至S / Rmount。 输出脉冲生成部（13）根据移位脉冲S / R1out〜S / Rmount的组合，生成输出脉冲SF1out〜SFnout。

公开(公告)号：US07821511B2

公开(公告)日：2010-10-26

申请号：US10557799

申请日：2004-05-14

申请人： Yoshiharu Nakajima ,  Yoshitoshi Kida

发明人： Yoshiharu Nakajima ,  Yoshitoshi Kida

IPC分类号： G09G5/00

CPC分类号： H02M3/073 ,  H02M2003/076

摘要： A supply voltage conversion circuit allowing fabrication of a charge pump circuit having a large current capability with a small area is provided. In a charge pump DC-DC converter (10) for converting a supply voltage VDD1 to a supply voltage VDD2, a level shifter (12) implements amplitude conversion to convert from a control pulse with amplitude of VSS-VDD1 to a control pulse with amplitude of VSS-VDD2. By using the control pulse having the converted amplitude as a pumping pulse, a flying capacitor (C11) is charged/discharged by MOS transistors (Qp11), and (Qn11) of a charge pump circuit (11), and switching of MOS transistors (Qn12), and (Qp12) coupled to the output of the flying capacitor (C11) is controlled.

摘要翻译： 提供了允许制造具有小面积的具有大电流能力的电荷泵电路的电源电压转换电路。 在用于将电源电压VDD1转换为电源电压VDD2的电荷泵DC-DC转换器（10）中，电平转换器（12）进行幅度转换，以将具有振幅为VSS-VDD1的控制脉冲转换成具有振幅的控制脉冲 的VSS-VDD2。 通过使用具有转换幅度的控制脉冲作为泵浦脉冲，由电荷泵电路（11）的MOS晶体管（Qp11）和（Qn11）对浮动电容器（C11）进行充电/放电，以及MOS晶体管 Qn12）和耦合到飞跨电容器（C11）的输出的（Qp12）。

公开(公告)号：US20090002083A1

公开(公告)日：2009-01-01

申请号：US12087273

申请日：2007-01-19

申请人： Yusuke Takahashi ,  Yoshitoshi Kida ,  Yoshiharu Nakajima

发明人： Yusuke Takahashi ,  Yoshitoshi Kida ,  Yoshiharu Nakajima

IPC分类号： H03L7/00 ,  G06F3/038

CPC分类号： H03K3/0315 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0439 ,  H03K3/84 ,  H03K2005/00247

摘要： An oscillation circuit, power supply circuit, display device using same, and electronic apparatus which can be built in a display panel without causing an increase of cost and do not need any adjustment work, each having a pulse generation portion 161 formed by an oscillator outputting rectangular wave signals having a frequency variation and a frequency variation correction portion 162 for suppressing output rectangular waves of the pulse generation portion 161 within a certain frequency range and outputting the same to a boosting circuit 163, wherein the frequency variation correction portion 162 includes an input pulse counter 1621 having n number of counters cascade connected and counting numbers of high level and low level periods of rectangular waves input from the pulse generation portion within a comparison input period, a counter value comparison circuit 1622 for generating a selection signal for selecting a last output from any counter among the cascade connected counters when the input pulse counter counts any number, and an output selection circuit 1623 for receiving the selection signal and outputting a corresponding counter value.

摘要翻译： 振荡电路，电源电路，使用它的显示装置以及可以内置在显示面板中而不引起成本增加并且不需要任何调整工作的电子设备，每个都具有由振荡器输出形成的脉冲产生部分161 具有频率变化的矩形波信号和频率变化校正部分162，用于在一定频率范围内抑制脉冲发生部分161的输出矩形波并将其输出到升压电路163，其中频率变化校正部分162包括输入 脉冲计数器1621，其具有在比较输入周期内从脉冲产生部分输入的n个级联的计数器级联连接和计数的高电平和低电平周期的矩形波;计数器值比较电路1622，用于产生用于选择最后一个 从串联连接的计数器之间的任何计数器输出 n输入脉冲计数器对任何数量进行计数，以及输出选择电路1623，用于接收选择信号并输出​​相应的计数器值。

公开(公告)号：US20070195038A1

公开(公告)日：2007-08-23

申请号：US11789279

申请日：2007-04-23

申请人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

发明人： Yoshitoshi Kida ,  Yoshiharu Nakajima ,  Toshikazu Maekawa

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3655 ,  G09G3/3688 ,  G09G2300/0876 ,  G09G2310/0245 ,  G09G2310/027 ,  G09G2310/06 ,  G09G2310/063 ,  G09G2320/0204 ,  G09G2320/0219 ,  G09G2320/0257 ,  G09G2330/026 ,  G09G2330/027

摘要： A liquid crystal display device enabling a reduction in size and costs associated with the system as a whole, starting to display images without image distortion at power on time, and turning the screen off without image retention at power off time, a method of controlling the liquid crystal display device, and a mobile terminal incorporating the liquid crystal display device as a screen display. On a glass substrate (11) provided with a display unit (12), peripheral drive circuits such as an interface circuit (13), a timing generator (14), a reference voltage driver (15), a CS driver (18), a VCOM driver (19), and a voltage regulation circuit (20), together with a horizontal driver (16) and a vertical driver (17) are disposed. When a display reset control pulse PCI is supplied from an external source, a predetermined voltage is written into pixels while a CS voltage and a VCOM voltage adjusted to the same level as that of a pixel voltage are applied to a common-electrode-side. This allows the screen to turn white in a normally white type liquid crystal display, and to turn black in a normally black type liquid crystal display. Image distortion at power on/off time can thus be prevented.

摘要翻译： 一种液晶显示装置，其能够与整个系统相关联地减小尺寸和成本，开始显示在通电时间没有图像失真的图像，并且在断电时关闭屏幕而不进行图像保持;控制方法 液晶显示装置和结合有液晶显示装置的移动终端作为画面显示。 在设置有显示单元（12）的玻璃基板（11）上，诸如接口电路（13），定时发生器（14），参考电压驱动器（15），CS驱动器（18）， 设置VCOM驱动器（19）和电压调节电路（20）以及水平驱动器（16）和垂直驱动器（17）。 当从外部源提供显示复位控制脉冲PCI时，将预定电压写入像素，同时将CS电压和VCOM电压调整到与像素电压相同的电平施加到共电极侧。 这允许屏幕在普通白色液晶显示器中变为白色，并且在常黑型液晶显示器中变黑。 因此可以防止电源开/关时的图像失真。