公开(公告)号：US06465340B1

公开(公告)日：2002-10-15

申请号：US09776734

申请日：2001-02-06

申请人： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

发明人： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L2221/1031

摘要： An interconnect structure and method of forming the same in which a first inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a via in the first dielectric layer. A second low k dielectric material is deposited within the via and over the etch stop layer to form a second dielectric layer over the via and the etch stop layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. A portion of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.

摘要翻译： 一种互连结构及其形成方法，其中第一无机低k电介质材料沉积在导电层上以形成第一介电层。 在第一电介质层上形成蚀刻停止层。 蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成通孔。 第二低k电介质材料沉积在通孔内和蚀刻停止层上方，以在通孔和蚀刻停止层之上形成第二电介质层。 再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽的一部分直接在通孔的上方。 重新打开的通孔和沟槽填充有导电材料。

公开(公告)号：US06429116B1

公开(公告)日：2002-08-06

申请号：US09778064

申请日：2001-02-07

申请人： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

发明人： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure and method of forming the same in which a diffusion barrier/etch stop layer is deposited over a conductive layer. An organic low k dielectric material is deposited over the diffusin barrier/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a slot via in the first dielectric layer. An inorganic low k dielectric material is deposited within the slot via and over the first dielectric layer to form a second dielectric layer over the slot via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. The trench extends in a direction that is normal to the length of the slot via. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.

摘要翻译： 一种互连结构及其形成方法，其中扩散阻挡/蚀刻停止层沉积在导电层上。 将有机低k电介质材料沉积在漫射阻挡层/蚀刻停止层上以形成第一介电层。 蚀刻第一介电层以在第一介电层中形成槽通孔。 无机低k电介质材料通过第一介电层上方和上方沉积在槽内，以在槽通孔和第一介电层上形成第二电介质层。 再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽沿与槽通孔的长度垂直的方向延伸。 沟槽的整个宽度直接在通孔上方。 重新打开的通孔和沟槽填充有导电材料。

公开(公告)号：US06383919B1

公开(公告)日：2002-05-07

申请号：US09778112

申请日：2001-02-07

申请人： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

发明人： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/31138 ,  H01L21/76808 ,  H01L2221/1031

摘要： An interconnect structure and method of forming the same in which a bottom anti-reflective coating/etch stop layer is deposited over a conductive layer. An organic low k dielectric material is deposited over the BARC/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a via in the first dielectric layer. An inorganic low k dielectric material is deposited within the via and over the first dielectric layer to form a second dielectric layer over the via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. A portion of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.

摘要翻译： 一种互连结构及其形成方法，其中底部抗反射涂层/蚀刻停止层沉积在导电层上。 在BARC /蚀刻停止层上沉积有机低k电介质材料以形成第一介电层。 蚀刻第一介电层以在第一介电层中形成通孔。 无机低k介电材料沉积在通孔内和第一介电层上方，以在通孔和第一介电层上方形成第二电介质层。 再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽的一部分直接在通孔的上方。 重新打开的通孔和沟槽填充有导电材料。

公开(公告)号：US06372635B1

公开(公告)日：2002-04-16

申请号：US09776736

申请日：2001-02-06

申请人： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

发明人： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L2221/1031 ,  Y10S977/827

摘要： An interconnect structure and method of forming the same in which a bottom anti-reflective coating/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the BARC/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a slot via in the first dielectric layer. An organic low k dielectric material is deposited within the slot via and over the first dielectric layer to form a second dielectric layer over the slot via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. The trench extends in a direction that is normal to the length of the slot via. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.

摘要翻译： 一种互连结构及其形成方法，其中底部抗反射涂层/蚀刻停止层沉积在导电层上。 无机低k介电材料沉积在BARC /蚀刻停止层上以形成第一介电层。 蚀刻第一介电层以在第一介电层中形成槽通孔。 有机低k电介质材料通过第一电介质层和第一介电层上方沉积在槽内，以在槽通孔和第一介电层上形成第二电介质层。 再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽沿与槽通孔的长度垂直的方向延伸。 沟槽的整个宽度直接在通孔上方。 重新打开的通孔和沟槽填充有导电材料。

公开(公告)号：US6060380A

公开(公告)日：2000-05-09

申请号：US187391

申请日：1998-11-06

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Simon Chan ,  Fei Wang

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Simon Chan ,  Fei Wang

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/31144 ,  H01L21/76813

摘要： A method for etching openings in an integrated circuit uses siliconoxynitride as a hardmask layer. Because of the relatively low reflectivity of siliconoxynitride, when a photoresist layer is deposited on the siliconoxynitride hardmask layer and is exposed to light, the photoresist layer is patterned more conformingly to a desired pattern. The present invention may be used to particular advantage for etching contiguous trench lines and via holes in a dual damascene etch process for small dimension integrated circuits.

摘要翻译： 用于蚀刻集成电路中的开口的方法使用硅氧氮化物作为硬掩模层。 由于硅氧氮化物的相对低的反射率，当光致抗蚀剂层沉积在硅氧氮化物硬掩模层上并暴露于光时，光致抗蚀剂层被图案更符合期望的图案。 本发明可以用于在用于小尺寸集成电路的双镶嵌蚀刻工艺中蚀刻连续沟槽线和通孔的特别优点。

公开(公告)号：US06423612B1

公开(公告)日：2002-07-23

申请号：US09604547

申请日：2000-06-26

申请人： Wenge Yang ,  John Jianshi Wang ,  Fei Wang

发明人： Wenge Yang ,  John Jianshi Wang ,  Fei Wang

IPC分类号： H01L21336

CPC分类号： H01L21/76224

摘要： A shallow trench isolation (STI) region is covered with a nitride layer. The nitride layer, advantageously, fills in gaps in the underlying dielectric layer, such as seams, thereby reducing leakage. The nitride layer may be patterned to form a spacer above the STI region which is used to define an opening in the polysilicon layer that is subsequently deposited. The polysilicon layer is etched back to expose the nitride spacer, which is then etched away in a controlled fashion. Thus, a small opening may be formed in the polysilicon layer. Further, because the polysilicon layer is etched back to the top of the nitride spacer, the polysilicon layer is planarized thereby reducing stringers in subsequent processing.

摘要翻译： 浅沟槽隔离（STI）区域被氮化物层覆盖。 有利地，氮化物层填充下面的介电层中的间隙，例如接缝，从而减少泄漏。 可以对氮化物层进行图案化以在STI区域上形成间隔物，其用于限定随后沉积的多晶硅层中的开口。 蚀刻多晶硅层以暴露氮化物间隔物，然后以受控的方式将其去掉。 因此，可以在多晶硅层中形成小开口。 此外，由于多晶硅层被回蚀刻到氮化物间隔物的顶部，所以多晶硅层被平坦化，从而在随后的处理中减少桁条。

公开(公告)号：US06420752B1

公开(公告)日：2002-07-16

申请号：US09502163

申请日：2000-02-11

申请人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

发明人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/115 ,  H01L2924/3011

摘要： A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

摘要翻译： 公开了一种用于最小化自动掺杂问题的半导体器件。 蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。 衬垫氧化物层直接形成在衬底上并且与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触并且用作介电层的自动掺杂势垒，以防止形成在衬底中的硼和磷 电介质层自动掺入源和漏极。

公开(公告)号：US06475847B1

公开(公告)日：2002-11-05

申请号：US10109526

申请日：2002-03-27

申请人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

发明人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

IPC分类号： H01L218238

CPC分类号： H01L27/11521 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/115 ,  H01L2924/3011

摘要： A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

摘要翻译： 公开了一种缩小半导体器件并最小化自动掺杂问题的方法。 蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。 衬垫氧化物层直接形成在衬底上并与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触，并且用作电介质层的自动掺杂势垒，以防止形成在衬底中的硼和磷 电介质层自动掺入源和漏极。

公开(公告)号：US06444530B1

公开(公告)日：2002-09-03

申请号：US09318429

申请日：1999-05-25

申请人： Hung-Sheng Chen ,  Unsoon Kim ,  Yu Sun ,  Chi Chang ,  Mark Ramsbey ,  Mark Randolph ,  Tatsuya Kajita ,  Angela Hui ,  Fei Wang ,  Mark Chang

发明人： Hung-Sheng Chen ,  Unsoon Kim ,  Yu Sun ,  Chi Chang ,  Mark Ramsbey ,  Mark Randolph ,  Tatsuya Kajita ,  Angela Hui ,  Fei Wang ,  Mark Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L2924/0002 ,  Y10T428/12542 ,  Y10T428/1259 ,  Y10T428/12625 ,  Y10T428/12778 ,  H01L2924/00

摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

摘要翻译： 在闪速存储器件中形成触点的方法利用局部互连处理技术。 局部互连处理技术允许接触件与存储器单元相关联的堆叠栅极对接或重叠。 接触可以包括钨。 堆叠的栅极被也覆盖绝缘间隔物的阻挡层覆盖。

公开(公告)号：US5907781A

公开(公告)日：1999-05-25

申请号：US49517

申请日：1998-03-27

申请人： Hung-Sheng Chen ,  Unsoon Kim ,  Yu Sun ,  Chi Chang ,  Mark Ramsbey ,  Mark Randolph ,  Tatsuya Kajita ,  Angela Hui ,  Fei Wang ,  Mark Chang

发明人： Hung-Sheng Chen ,  Unsoon Kim ,  Yu Sun ,  Chi Chang ,  Mark Ramsbey ,  Mark Randolph ,  Tatsuya Kajita ,  Angela Hui ,  Fei Wang ,  Mark Chang

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/335

CPC分类号： H01L21/76897 ,  H01L21/76895

摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.