公开(公告)号：US08823002B2

公开(公告)日：2014-09-02

申请号：US13510315

申请日：2010-08-23

申请人： Michiko Takei ,  Tohru Okabe ,  Tetsuya Aita ,  Tsuyoshi Inoue ,  Yoshiyuki Harumoto ,  Takeshi Yaneda

发明人： Michiko Takei ,  Tohru Okabe ,  Tetsuya Aita ,  Tsuyoshi Inoue ,  Yoshiyuki Harumoto ,  Takeshi Yaneda

IPC分类号： H01L31/036 ,  H01L21/268 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L21/268 ,  H01L27/1229 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78678

摘要： An object of this invention is to provide a semiconductor device in which TFTs with high mobility are arranged in both of display and peripheral circuit areas. A semiconductor device fabricating method according to the present invention includes the steps of: irradiating an amorphous silicon layer (34) with energy, thereby obtaining a microcrystalline silicon layer; and forming a doped semiconductor layer (35) on the amorphous silicon layer (34). In the step of irradiating, the amorphous silicon layer (34) is irradiated with energy that has a first quantity, thereby forming a first microcrystalline silicon layer (34A) including a channel layer for a first TFT (30A), and is also irradiated with energy that has a second quantity, which is larger than the first quantity, thereby forming a second microcrystalline silicon layer (34B) including a channel layer for a second TFT (30B).

摘要翻译： 本发明的目的是提供一种半导体器件，其中具有高迁移率的TFT被布置在显示器和外围电路区域中。 根据本发明的半导体器件制造方法包括以下步骤：用能量照射非晶硅层（34），从而获得微晶硅层; 以及在所述非晶硅层（34）上形成掺杂半导体层（35）。 在照射步骤中，用具有第一量的能量照射非晶硅层（34），由此形成包括用于第一TFT（30A）的沟道层的第一微晶硅层（34A），并且还用 具有大于第一量的第二量的能量，由此形成包括用于第二TFT（30B）的沟道层的第二微晶硅层（34B）。

公开(公告)号：US08441016B2

公开(公告)日：2013-05-14

申请号：US13383077

申请日：2010-07-08

申请人： Tsuyoshi Inoue ,  Tohru Okabe ,  Tetsuya Aita ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Takeshi Yaneda

发明人： Tsuyoshi Inoue ,  Tohru Okabe ,  Tetsuya Aita ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Takeshi Yaneda

IPC分类号： H01L33/08

CPC分类号： H01L29/78627 ,  G02F1/1368 ,  G02F2202/104 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78624

摘要： Disclosed is a high-quality, efficiently manufacturable thin film transistor in which leakage current is minimized. The thin film transistor is provided with a semiconductor layer (34) that contains a channel region (34C) having a microcrystalline semiconductor; source and drain contact layers (35S and 35D) that contains impurities; a first source metal layer (36S) and a first drain metal layer (36D), and a second source metal layer (37S) and a second drain metal layer (37D). The end portion of the second metal source layer (37S) is located at a position receded from the end portion of the first metal source layer (36S) and the end portion of the second drain metal layer (37D) is located at a position receded from the end portion of the first drain metal layer (36D). The semiconductor layer (34) contains low concentration impurity diffusion regions formed near the end portions of the aforementioned source contact layer (35S) and drain contact layer (35D).

摘要翻译： 公开了一种其中泄漏电流最小化的高品质，高效制造的薄膜晶体管。 薄膜晶体管设置有包含具有微晶半导体的沟道区（34C）的半导体层（34） 源极和漏极接触层（35S和35D），其含有杂质; 第一源极金属层（36S）和第一漏极金属层（36D）以及第二源极金属层（37S）和第二漏极金属层（37D）。 第二金属源层（37S）的端部位于从第一金属源层（36S）的端部退出的位置，第二漏极金属层（37D）的端部位于退出的位置 从第一漏极金属层（36D）的端部开始。 半导体层（34）包含在上述源极接触层（35S）和漏极接触层（35D）的端部附近形成的低浓度杂质扩散区域。

公开(公告)号：US20120228621A1

公开(公告)日：2012-09-13

申请号：US13510315

申请日：2010-08-23

申请人： Michiko Takei ,  Tohru Okabe ,  Tetsuya Aita ,  Tsuyoshi Inoue ,  Yoshiyuki Harumoto ,  Takeshi Yaneda

发明人： Michiko Takei ,  Tohru Okabe ,  Tetsuya Aita ,  Tsuyoshi Inoue ,  Yoshiyuki Harumoto ,  Takeshi Yaneda

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L21/268 ,  H01L27/1229 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78678

摘要： An object of this invention is to provide a semiconductor device in which TFTs with high mobility are arranged in both of display and peripheral circuit areas. A semiconductor device fabricating method according to the present invention includes the steps of: irradiating an amorphous silicon layer (34) with energy, thereby obtaining a microcrystalline silicon layer; and forming a doped semiconductor layer (35) on the amorphous silicon layer (34). In the step of irradiating, the amorphous silicon layer (34) is irradiated with energy that has a first quantity, thereby forming a first microcrystalline silicon layer (34A) including a channel layer for a first TFT (30A), and is also irradiated with energy that has a second quantity, which is larger than the first quantity, thereby forming a second microcrystalline silicon layer (34B) including a channel layer for a second TFT (30B).

摘要翻译： 本发明的目的是提供一种半导体器件，其中具有高迁移率的TFT被布置在显示器和外围电路区域中。 根据本发明的半导体器件制造方法包括以下步骤：用能量照射非晶硅层（34），从而获得微晶硅层; 以及在所述非晶硅层（34）上形成掺杂半导体层（35）。 在照射步骤中，用具有第一量的能量照射非晶硅层（34），由此形成包括用于第一TFT（30A）的沟道层的第一微晶硅层（34A），并且还用 具有大于第一量的第二量的能量，由此形成包括用于第二TFT（30B）的沟道层的第二微晶硅层（34B）。

公开(公告)号：US20120104406A1

公开(公告)日：2012-05-03

申请号：US13383077

申请日：2010-07-08

申请人： Tsuyoshi Inoue ,  Tohru Okabe ,  Tetsuya Aita ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Takeshi Yaneda

发明人： Tsuyoshi Inoue ,  Tohru Okabe ,  Tetsuya Aita ,  Michiko Takei ,  Yoshiyuki Harumoto ,  Takeshi Yaneda

IPC分类号： H01L33/08

CPC分类号： H01L29/78627 ,  G02F1/1368 ,  G02F2202/104 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78624

摘要： Disclosed is a high-quality, efficiently manufacturable thin film transistor in which leakage current is minimized. The thin film transistor is provided with a semiconductor layer (34) that contains a channel region (34C) having a microcrystalline semiconductor; source and drain contact layers (35S and 35D) that contains impurities; a first source metal layer (36S) and a first drain metal layer (36D), and a second source metal layer (37S) and a second drain metal layer (37D). The end portion of the second metal source layer (37S) is located at a position receded from the end portion of the first metal source layer (36S) and the end portion of the second drain metal layer (37D) is located at a position receded from the end portion of the first drain metal layer (36D). The semiconductor layer (34) contains low concentration impurity diffusion regions formed near the end portions of the aforementioned source contact layer (35S) and drain contact layer (35D).

摘要翻译： 公开了一种其中泄漏电流最小化的高品质，高效制造的薄膜晶体管。 薄膜晶体管设置有包含具有微晶半导体的沟道区（34C）的半导体层（34） 源极和漏极接触层（35S和35D），其含有杂质; 第一源极金属层（36S）和第一漏极金属层（36D）以及第二源极金属层（37S）和第二漏极金属层（37D）。 第二金属源层（37S）的端部位于从第一金属源层（36S）的端部退出的位置，第二漏极金属层（37D）的端部位于退出的位置 从第一漏极金属层（36D）的端部开始。 半导体层（34）包含在上述源极接触层（35S）和漏极接触层（35D）的端部附近形成的低浓度杂质扩散区域。

公开(公告)号：US20120154287A1

公开(公告)日：2012-06-21

申请号：US13392704

申请日：2010-08-27

申请人： Michiko Takei

发明人： Michiko Takei

IPC分类号： G06F3/02

CPC分类号： G06F15/0225 ,  G06F3/0237 ,  G06F3/0238 ,  H03M11/04 ,  H04M1/0235 ,  H04M1/56 ,  H04M1/72522 ,  H04M2250/18 ,  H04M2250/70

摘要： Disclosed are a handheld electronic device and a display method for a handheld electronic device whereby, when an initialization screen is displayed by a display unit, it is possible, in response to user input, to display symbols reflecting the intent of the user. The disclosed handheld electronic device is provided with: a user input unit (22) having a first key to which a symbol of a first type is allocated and a symbol of a second type is not allocated, and a second key to which a symbol of the first type and a symbol of the second type are both allocated; a display unit (12) that, upon input via the user input unit (22), displays a symbol of the first type and/or a symbol of the second type; and a control unit (35) that controls what the display unit (12) displays. While an initialization screen is being displayed by the display unit (12), if the first key is pressed, the control unit (35) has the display unit (12) display the symbol of the first type which is allocated to the pressed first key, and if the second key is pressed, the control unit (35) has the display unit (12) display the symbol of the first type and the symbol of the second type which are allocated to the pressed second key.

摘要翻译： 公开了一种手持电子设备和用于手持电子设备的显示方法，其中当显示单元显示初始化屏幕时，可以响应于用户输入显示反映用户意图的符号。 所公开的手持电子设备具有：具有第一密钥的用户输入单元（22），第一密钥被分配给第一类型的符号，并且没有分配第二类型的符号;以及第二密钥，其中符号 第一类型和第二类型的符号都被分配; 显示单元（12），其经由用户输入单元（22）输入时，显示第一类型的符号和/或第二类型的符号; 以及控制显示单元（12）显示什么的控制单元（35）。 当显示单元（12）正在显示初始化屏幕时，如果第一键被按下，则控制单元（35）具有显示单元（12），显示分配给按下的第一键的第一类型的符号 并且如果按下第二个键，则控制单元（35）具有显示单元（12），显示分配给按下的第二键的第一类型的符号和第二类型的符号。

公开(公告)号：US20110241174A1

公开(公告)日：2011-10-06

申请号：US13139988

申请日：2009-08-21

申请人： Michiko Takei ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Shin Matsumoto ,  Kazuo Nakagawa ,  Yutaka Takafuji

发明人： Michiko Takei ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Shin Matsumoto ,  Kazuo Nakagawa ,  Yutaka Takafuji

IPC分类号： H01L21/301 ,  H01L29/06

CPC分类号： H01L27/1266 ,  H01L27/1214 ,  H01L29/66772 ,  H01L29/78636

摘要： Provided is a semiconductor device manufacturing method wherein the following steps are performed; a step of forming at least a part of an element on a base body layer, a step of forming a peeling layer, a step of forming a planarizing film; a step of forming a die by separating the base body layer at a separating region; a step of bonding the die to a substrate by bonding the die on the planarizing film; and a step of peeling and removing a part of the base body layer along the peeling layer. Prior to the step of forming the die, a step of forming a groove opened on the surface of the planarizing film such that at least a part of the separating region is included on the bottom surface of the groove, and forming the die such that the die has a polygonal outer shape wherein all the internal angles are obtuse by forming the groove is performed.

摘要翻译： 提供一种其中执行以下步骤的半导体器件制造方法; 在基体层上形成元素的至少一部分的步骤，形成剥离层的步骤，形成平坦化膜的步骤; 通过在分离区域分离基体层而形成模具的步骤; 通过将该模具接合在平坦化膜上而将芯片接合到基板的步骤; 以及沿剥离层剥离和去除基体层的一部分的步骤。 在成型模具的步骤之前，形成在平坦化膜的表面上开口的槽，使得至少一部分分离区域包含在槽的底表面上，并且形成模具，使得 模具具有多边形外形，其中通过形成凹槽来执行所有内角都是钝的。

公开(公告)号：US20100283103A1

公开(公告)日：2010-11-11

申请号：US12745497

申请日：2008-11-14

申请人： Michiko Takei ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Masao Moriguchi ,  Yutaka Takafuji

发明人： Michiko Takei ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Masao Moriguchi ,  Yutaka Takafuji

IPC分类号： H01L29/786 ,  H01L21/762

CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214

摘要： A method for manufacturing a semiconductor device includes: a first step of forming a base layer, which includes an element portion having a gate electrode and a flat interlayer insulating film formed so as to cover the gate electrode; a second step of ion implanting a delamination material into the base layer to form a delamination layer; a third step of bonding the base layer to a substrate; and a fourth step of separating and removing a part of the base layer along the delamination layer. An implantation depth of the delamination material in the gate electrode is substantially the same as that of the delamination material in the interlayer insulating film.

摘要翻译： 一种制造半导体器件的方法包括：形成基底层的第一步骤，其包括具有栅电极的元件部分和形成为覆盖栅电极的平坦层间绝缘膜; 将分层材料离子注入基层以形成分层的第二步骤; 将基底层粘合到基底上的第三步骤; 以及沿剥离层分离除去基底层的一部分的第四工序。 栅电极中的分层材料的注入深度与层间绝缘膜中的分层材料的植入深度基本相同。

公开(公告)号：US20100148261A1

公开(公告)日：2010-06-17

申请号：US12159582

申请日：2006-10-13

申请人： Yasumori Fukushima ,  Yutaka Takafuji ,  Michiko Takei ,  Kazuhide Tomiyasu

发明人： Yasumori Fukushima ,  Yutaka Takafuji ,  Michiko Takei ,  Kazuhide Tomiyasu

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/76254 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/12 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a uniform thickness; a second planarization film formation step of forming a second planarization film between the first planarization films to be coplanar with a surface of the first planarization film; a peeling layer formation step of forming a peeling layer by ion implantation of a peeling material into the base layer via the first planarization film or the second planarization film; and a separation step of separating part of the base layer along the peeling layer.

摘要翻译： 本发明的方法包括：第一平坦化膜形成步骤，在第二区域的平坦部分的至少一部分中形成具有均匀厚度的第一平坦化膜; 第二平坦化膜形成步骤，在所述第一平坦化膜之间形成与所述第一平坦化膜的表面共面的第二平坦化膜; 剥离层形成步骤，通过经由第一平坦化膜或第二平坦化膜将剥离材料离子注入基底层来形成剥离层; 以及分离步骤，用于沿着剥离层分离基底层的一部分。

公开(公告)号：US20090001504A1

公开(公告)日：2009-01-01

申请号：US12162568

申请日：2006-12-13

申请人： Michiko Takei ,  Kazuhide Tomiyasu ,  Yasumori Fukushima ,  Yutaka Takafuji

发明人： Michiko Takei ,  Kazuhide Tomiyasu ,  Yasumori Fukushima ,  Yutaka Takafuji

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L27/1214 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1266 ,  H01L29/66772 ,  H01L29/78603

摘要： A transistor formed on a monocrystalline Si wafer is temporarily transferred onto a first temporary supporting substrate. The first temporarily supporting substrate is heat-treated at high heat so as to repair crystal defects generated in a transistor channel of the monocrystalline Si wafer when transferring the transistor. The transistor is then made into a chip and transferred onto a TFT substrate. In order to transfer the transistor which has been once separated from the monocrystalline Si wafer, a different method from a stripping method utilizing ion doping is employed.

摘要翻译： 形成在单晶Si晶片上的晶体管暂时转移到第一临时支撑衬底上。 第一临时支撑基板在高温下热处理，以便在传输晶体管时修复在单晶硅晶片的晶体管沟道中产生的晶体缺陷。 然后将晶体管制成芯片并转移到TFT基板上。 为了将已经从单晶Si晶片分离出来的晶体管转移，使用与使用离子掺杂的剥离方法不同的方法。

公开(公告)号：US06677222B1

公开(公告)日：2004-01-13

申请号：US09637276

申请日：2000-08-11

申请人： Yasuyoshi Mishima ,  Katsuyuki Suga ,  Michiko Takei ,  Akito Hara

发明人： Yasuyoshi Mishima ,  Katsuyuki Suga ,  Michiko Takei ,  Akito Hara

IPC分类号： H01L2120

CPC分类号： H01L21/02675 ,  H01L21/2022 ,  H01L21/2026

摘要： A first layer made of polysilicon is formed on the surface of an underlying substrate. The surface of the first layer is exposed to an environment which etches silicon oxide. If the surface of the first layer is covered with a silicon oxide film, the silicon oxide film is removed. An energy is supplied to the first layer, the energy allowing silicon crystal to re-grow. Solid phase growth of silicon occurs in the first layer to planarize the surface thereof. A polysilicon film having small root mean square of roughness can be formed.

摘要翻译： 在下面的衬底的表面上形成由多晶硅制成的第一层。 第一层的表面暴露于蚀刻氧化硅的环境中。 如果第一层的表面被氧化硅膜覆盖，则去除氧化硅膜。 能量被供应到第一层，能量允许硅晶体再生长。 在第一层中发生硅的固相生长以平坦化其表面。 可以形成具有小的粗糙度均方根的多晶硅膜。