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    Active matrix substrate and display device including the same
    1.
    发明授权
    Active matrix substrate and display device including the same 有权
    有源矩阵基板和包括其的显示装置

    公开(公告)号：US09245904B2

    公开(公告)日：2016-01-26

    申请号：US14118587

    申请日：2012-06-15

    申请人： Yasumori Fukushima

    发明人： Yasumori Fukushima

    IPC分类号： H01L27/12 ,  G02F1/1333 ,  G02F1/1362

    CPC分类号： H01L27/1218 ,  G02F1/133305 ,  G02F1/133345 ,  G02F1/1362 ,  Y10T428/2495

    摘要： The thickness of a rear surface-side inorganic film (9) formed from the same material as that of each of front surface-side inorganic films (11, 13, and 16) and provided at a rear surface side of a resin substrate (10) having a heat resistance is set in a predetermined range with respect to the total thickness of the front surface-side inorganic films (11, 13, and 16) so that the curvature diameter calculated based on the linear elastic modulus, the coefficient of linear expansion, and the thickness of the resin substrate (10); the linear elastic moduli, the coefficients of linear expansion, and the total thickness of the front surface-side inorganic films (11, 13, and 16); and the linear elastic modulus, the coefficient of linear expansion, and the thickness of the rear surface-side inorganic film (9) is 20 mm or more or −20 mm or less.

    摘要翻译： 由与前表面侧无机膜（11,13和16）相同的材料形成并设置在树脂基板（10）的背面侧的后表面侧无机膜（9）的厚度 ）相对于前表面侧无机膜（11,13和16）的总厚度设定在预定范围内，使得基于线性弹性模量计算的曲率直径，线性系数 膨胀和树脂基板（10）的厚度; 线性弹性模量，线膨胀系数和前表面侧无机膜（11,13和16）的总厚度; 并且后表面侧无机膜（9）的线弹性模量，线膨胀系数和厚度为20mm以上或-20mm以下。

    Semiconductor device and method for manufacturing same
    2.
    发明授权
    Semiconductor device and method for manufacturing same 有权
    半导体装置及其制造方法

    公开(公告)号：US08361882B2

    公开(公告)日：2013-01-29

    申请号：US13139988

    申请日：2009-08-21

    申请人： Michiko Takei ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Shin Matsumoto ,  Kazuo Nakagawa ,  Yutaka Takafuji

    发明人： Michiko Takei ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Shin Matsumoto ,  Kazuo Nakagawa ,  Yutaka Takafuji

    IPC分类号： H01L21/30 ,  H01L29/06

    CPC分类号： H01L27/1266 ,  H01L27/1214 ,  H01L29/66772 ,  H01L29/78636

    摘要： Provided is a semiconductor device manufacturing method wherein the following steps are performed; a step of forming at least a part of an element on a base body layer, a step of forming a peeling layer, a step of forming a planarizing film; a step of forming a die by separating the base body layer at a separating region; a step of bonding the die to a substrate by bonding the die on the planarizing film; and a step of peeling and removing a part of the base body layer along the peeling layer. Prior to the step of forming the die, a step of forming a groove opened on the surface of the planarizing film such that at least a part of the separating region is included on the bottom surface of the groove, and forming the die such that the die has a polygonal outer shape wherein all the internal angles are obtuse by forming the groove is performed.

    摘要翻译： 提供一种其中执行以下步骤的半导体器件制造方法; 在基体层上形成元素的至少一部分的步骤，形成剥离层的步骤，形成平坦化膜的步骤; 通过在分离区域分离基体层而形成模具的步骤; 通过将该模具接合在平坦化膜上而将芯片接合到基板的步骤; 以及沿剥离层剥离和去除基体层的一部分的步骤。 在成形模具的步骤之前，形成在平坦化膜的表面上开口的槽，使得至少一部分分离区域包含在槽的底面上，并且形成模具，使得 模具具有多边形外形，其中通过形成凹槽来执行所有内角都是钝的。

    Method for producing semiconductor device and semiconductor device produced by same method
    3.
    发明授权
    Method for producing semiconductor device and semiconductor device produced by same method 有权
    通过相同方法制造半导体器件和半导体器件的方法

    公开(公告)号：US08207046B2

    公开(公告)日：2012-06-26

    申请号：US12682221

    申请日：2008-10-21

    申请人： Michiko Takei ,  Shin Matsumoto ,  Yasumori Fukushima ,  Yutaka Takafuji

    发明人： Michiko Takei ,  Shin Matsumoto ,  Yasumori Fukushima ,  Yutaka Takafuji

    IPC分类号： H01L21/02

    CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772

    摘要： To prevent bubbles from occurring along a transfer interface, the present method includes the steps of: forming a peeled layer 10 in a transferred member 6 by implanting a peeled-layer forming substance into the transferred member 6; forming a planar surface in the transferred member 6 by planarizing a surface of the transferred member 6; forming a composite including the transferred member 6 and a glass substrate 2 by directly combining the transferred member 6 via the planar surface with a surface of the glass substrate 2; and peeling a part of the transferred member 6 from the composite along the peeled layer 10 serving as an interface by heat-treating the composite.

    摘要翻译： 为了防止沿着转移界面发生气泡，本方法包括以下步骤：通过将剥离层形成物质注入到被转印元件6中，在转印元件6中形成剥离层10; 通过使转印部件6的表面平坦化，在被转印部件6中形成平面; 通过经由平面表面直接将转印部件6与玻璃基板2的表面直接组合，形成包括转印部件6和玻璃基板2的复合体; 以及通过热处理复合材料，沿着作为界面的剥离层10将复合材料的一部分从复合材料剥离。

    Method for fabricating semiconductor device and semiconductor device with separation along peeling layer
    7.
    发明授权
    Method for fabricating semiconductor device and semiconductor device with separation along peeling layer 有权
    半导体器件制造方法和沿着剥离层分离的半导体器件

    公开(公告)号：US08017492B2

    公开(公告)日：2011-09-13

    申请号：US12222598

    申请日：2008-08-12

    申请人： Yasumori Fukushima ,  Masao Moriguchi ,  Yutaka Takafuji

    发明人： Yasumori Fukushima ,  Masao Moriguchi ,  Yutaka Takafuji

    IPC分类号： H01L21/76

    CPC分类号： H01L21/84 ,  H01L21/32 ,  H01L21/76254 ,  H01L27/1203 ,  H01L29/78654

    摘要： A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer.

    摘要翻译： 根据本发明的制造半导体器件的方法是一种半导体器件的制造方法，该半导体器件包括：衬底层，该衬底层包括多个第一区域，每个第一区域具有有源区域和多个第二区域， 地区。 制造方法包括隔离绝缘膜形成步骤，在每个第二区域中形成隔离绝缘膜，使得隔离绝缘膜的表面变得与覆盖有源区域的栅极氧化物膜的表面相同的高度 剥离层形成步骤，在隔离绝缘膜形成步骤之后，通过将氢离子注入到衬底层中形成剥离层，以及分离步骤，用于沿剥离层分离衬底层的一部分。

    Methods for producing a semiconductor device having planarization films
    8.
    发明授权
    Methods for producing a semiconductor device having planarization films 有权
    具有平坦化膜的半导体器件的制造方法

    公开(公告)号：US08008205B2

    公开(公告)日：2011-08-30

    申请号：US12159582

    申请日：2006-10-13

    申请人： Yasumori Fukushima ,  Yutaka Takafuji ,  Michiko Takei ,  Kazuhide Tomiyasu

    发明人： Yasumori Fukushima ,  Yutaka Takafuji ,  Michiko Takei ,  Kazuhide Tomiyasu

    IPC分类号： H01L21/311

    CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/76254 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/12 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a uniform thickness; a second planarization film formation step of forming a second planarization film between the first planarization films to be coplanar with a surface of the first planarization film; a peeling layer formation step of forming a peeling layer by ion implantation of a peeling material into the base layer via the first planarization film or the second planarization film; and a separation step of separating part of the base layer along the peeling layer.

    摘要翻译： 本发明的方法包括：第一平坦化膜形成步骤，在第二区域的平坦部分的至少一部分中形成具有均匀厚度的第一平坦化膜; 第二平坦化膜形成步骤，在所述第一平坦化膜之间形成与所述第一平坦化膜的表面共面的第二平坦化膜; 剥离层形成步骤，通过经由第一平坦化膜或第二平坦化膜将剥离材料离子注入基底层来形成剥离层; 以及分离步骤，用于沿着剥离层分离基底层的一部分。

    Semiconductor Device Fabrication Method And Semiconductor Device
    9.
    发明申请
    Semiconductor Device Fabrication Method And Semiconductor Device 有权
    半导体器件制造方法和半导体器件

    公开(公告)号：US20080128807A1

    公开(公告)日：2008-06-05

    申请号：US11792487

    申请日：2005-11-15

    申请人： Yasumori Fukushima ,  Yutaka Takafuji ,  Masao Moriguchi

    发明人： Yasumori Fukushima ,  Yutaka Takafuji ,  Masao Moriguchi

    IPC分类号： H01L27/00 ,  H01L21/00

    CPC分类号： H01L27/1203 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/265 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76254 ,  H01L21/84 ,  H01L29/7833

    摘要： In fabricating a semiconductor device, an element forming surface formation step of forming a plurality of element forming surfaces of different heights on a semiconductor layer to have different levels, a semiconductor element formation step of forming a plurality of semiconductor elements and, one in each of a corresponding number of regions of the semiconductor layer, each region including an associated one of the plurality of element forming surfaces, a level-difference compensation insulating film formation step of forming a level-difference compensation insulating film on the semiconductor layer to cover the semiconductor elements and have a surface with different levels along the element forming surfaces, a release layer formation step of forming a release layer in the semiconductor layer by ion-implanting a peeling material through the level-difference compensation insulating film into the semiconductor layer, and a separation step of separating part of the semiconductor layer along the release layer are performed.

    摘要翻译： 在制造半导体器件时，在半导体层上形成具有不同高度的多个元件形成表面以形成不同电平的元件形成表面形成步骤，形成多个半导体元件的半导体元件形成步骤和 所述半导体层的相应数量的区域，每个区域包括所述多个元件形成表面中的相关联的一个元件形成表面;电平差补偿绝缘膜形成步骤，在所述半导体层上形成电平差补偿绝缘膜以覆盖所述半导体 元件，并且具有沿着元件形成表面具有不同水平的表面;剥离层形成步骤，通过将剥离材料通过电位差补偿绝缘膜离子注入到半导体层中而在半导体层中形成剥离层，以及 分离半导体层的一部分的分离步骤 沿着释放层进行。

    Semiconductor substrate, semiconductor device, and manufacturing methods for them
    10.
    发明申请
    Semiconductor substrate, semiconductor device, and manufacturing methods for them 有权
    半导体衬底，半导体器件及其制造方法

    公开(公告)号：US20050245046A1

    公开(公告)日：2005-11-03

    申请号：US11086680

    申请日：2005-03-23

    申请人： Yutaka Takafuji ,  Yasumori Fukushima ,  Masao Moriguchi

    发明人： Yutaka Takafuji ,  Yasumori Fukushima ,  Masao Moriguchi

    IPC分类号： G02F1/1368 ,  G02F1/136 ,  G09F9/30 ,  G09G3/00 ,  H01L21/00 ,  H01L21/02 ,  H01L21/316 ,  H01L21/336 ,  H01L21/469 ,  H01L21/76 ,  H01L21/762 ,  H01L21/77 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/12 ,  H01L29/00 ,  H01L29/786

    CPC分类号： H01L27/1266 ,  H01L21/76202 ,  H01L21/76254 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/78603 ,  H01L29/78609

    摘要： The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film. On this account, on fabricating the semiconductor device having a high-performance integration system by forming the non-singlecrystalline Si semiconductor element and the singlecrystalline Si semiconductor element on the large insulating substrate, the process for making the singlecrystalline Si is simplified. Further, the foregoing arrangement provides a semiconductor substrate and a fabrication method thereof, which ensures device isolation of the minute singlecrystalline Si semiconductor element without highly-accurate photolithography, when the singlecrystalline Si semiconductor element is transferred onto the large insulating substrate.

    摘要翻译： 本发明提供一种半导体衬底，其包括单晶Si衬底，其包括具有沟道区，源极区和漏极区的有源层，所述单晶Si衬底包括至少部分不包含阱的器件结构 结构或通道停止区域; 形成在单晶Si衬底上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; LOCOS氧化物膜的厚度大于栅极绝缘膜的厚度，LOCOS氧化物膜通过围绕有源层而形成在单晶Si衬底上; 以及形成在栅电极和LOCOS氧化物膜上的绝缘膜。 因此，通过在大的绝缘基板上形成非单晶Si半导体元件和单晶Si半导体元件来制造具有高性能的集成系统的半导体器件，简化了制造单晶硅的工艺。 此外，上述结构提供半导体衬底及其制造方法，当将单晶硅半导体元件转印到大绝缘衬底上时，确保了微单晶Si半导体元件的器件隔离而没有高精度光刻。