公开(公告)号：US20110242892A1

公开(公告)日：2011-10-06

申请号：US13161147

申请日：2011-06-15

申请人： Yuko NAMIKI ,  Takuya Futatsuyama ,  Yuui Shimizu

发明人： Yuko NAMIKI ,  Takuya Futatsuyama ,  Yuui Shimizu

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.

摘要翻译： 一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。

公开(公告)号：US07907446B2

公开(公告)日：2011-03-15

申请号：US12266734

申请日：2008-11-07

申请人： Yuui Shimizu ,  Toshiaki Edahiro

发明人： Yuui Shimizu ,  Toshiaki Edahiro

IPC分类号： G11C16/04 ,  G11C8/00 ,  G11C11/34 ,  G11C16/06

CPC分类号： G11C8/08 ,  G11C8/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621

摘要： This disclosure concerns a memory including cell blocks, wherein in a first write sequence for writing data to a first cell block, drivers write the data only to memory cells arranged in a form of a checkered flag among the memory cells included in the first cell block, in a second write sequence for writing the data from the first cell block to a second cell block, the drivers write the data to all memory cells connected to a word line selected in the second cell block, and when the data is read from the first cell block or at a time of data verification when data is written to the first cell block, the word line drivers simultaneously apply a read voltage to two adjacent word lines, and the sense amplifiers detects the data in the memory cells connected to the two word lines.

摘要翻译： 本公开涉及包括单元块的存储器，其中在用于将数据写入第一单元块的第一写入序列中，驱动器将数据仅写入到以包括在第一单元块中的存储单元中的格状标志形式布置的存储单元 在用于将数据从第一单元块写入第二单元块的第二写入序列中，驱动器将数据写入连接到在第二单元块中选择的字线的所有存储器单元，并且当数据从 第一单元块，或者当数据被写入第一单元块时的数据验证时，字线驱动器同时向两个相邻的字线施加读取电压，并且读出放大器检测连接到两个单元的存储单元中的数据 字线。

公开(公告)号：US07864563B2

公开(公告)日：2011-01-04

申请号：US11863997

申请日：2007-09-28

申请人： Yuui Shimizu ,  Tsuneo Inaba

发明人： Yuui Shimizu ,  Tsuneo Inaba

IPC分类号： G11C11/02 ,  G11C11/14 ,  G11C11/15 ,  G11C7/14

CPC分类号： G11C29/52 ,  G11C11/16 ,  G11C2029/0409

摘要： A magnetic random access memory according to an example of the invention comprises a first reference bit line shared by first reference cells, a second reference bit line shared by second reference cells, a first driver-sinker to feed a first writing current, a second driver-sinker to feed a second writing current, and a control circuit which checks data stored in the first and second reference cells line by line, and executes writing simultaneously to all of the first and second reference cells by a uniaxial writing when the data is broken.

摘要翻译： 根据本发明的示例的磁随机存取存储器包括由第一参考单元共享的第一参考位线，由第二参考单元共享的第二参考位线，用于馈送第一写入电流的第一驱动器沉降器，第二驱动器 用于馈送第二写入电流的控制电路，以及一行一行地检查存储在第一和第二参考单元中的数据的控制电路，并且当数据被破坏时通过单轴写入同时执行对所有第一和第二参考单元的写入 。

公开(公告)号：US07859881B2

公开(公告)日：2010-12-28

申请号：US11672261

申请日：2007-02-07

申请人： Yoshihisa Iwata ,  Katsuyuki Fujita ,  Yuui Shimizu

发明人： Yoshihisa Iwata ,  Katsuyuki Fujita ,  Yuui Shimizu

IPC分类号： G11C19/00

CPC分类号： G11C19/0841 ,  G11C5/02 ,  G11C11/14 ,  G11C21/00 ,  Y10S977/933

摘要： A magnetic memory device includes a first magnetic line which has a plurality of cells made of magnetic domains partitioned by domain walls, and in which information is recorded in each cell, a first write element formed at one end portion of the first magnetic line, and a first read element formed at the other end portion of the first magnetic line.

摘要翻译： 一种磁存储器件包括：第一磁线，其具有由畴壁分隔的磁畴构成的多个单元，并且其中信息被记录在每个单元中，形成在第一磁线的一个端部处的第一写入元件，以及 形成在第一磁性线的另一端部的第一读取元件。

公开(公告)号：US07835210B2

公开(公告)日：2010-11-16

申请号：US11846985

申请日：2007-08-29

申请人： Yuui Shimizu

发明人： Yuui Shimizu

IPC分类号： G11C7/02

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/1673 ,  H01L27/24

摘要： A magnetic random access memory includes a memory element having a first fixed layer, a first recording layer, and a first nonmagnetic layer, a first reference element having a second fixed layer, a second recording layer, and a second nonmagnetic layer, antiparallel data being written in the first reference element, a second reference element making a pair with the first reference element, and having a third fixed layer, a third recording layer, and a third nonmagnetic layer, parallel data being written in the second reference element, and a current source which, when a read operation is performed, supplies a current from the second fixed layer to the second recording layer in the first reference element, and supplies the current from the third recording layer to the third fixed layer in the second reference element.

摘要翻译： 磁性随机存取存储器包括具有第一固定层，第一记录层和第一非磁性层的存储元件，具有第二固定层，第二记录层和第二非磁性层的第一参考元件，反平行数据 写入第一参考元素中的第二参考元素，与第一参考元素成对配对的第二参考元素，并具有第三固定层，第三记录层和第三非磁性层，并行数据被写入第二参考元素中，以及 电流源，当执行读取操作时，将来自第二固定层的电流提供给第一参考元件中的第二记录层，并将电流从第三记录层提供给第二参考元件中的第三固定层。

公开(公告)号：US20090238003A1

公开(公告)日：2009-09-24

申请号：US12363963

申请日：2009-02-02

申请人： Yuko NAMIKI ,  Takuya Futatsuyama ,  Yuui Shimizu

发明人： Yuko NAMIKI ,  Takuya Futatsuyama ,  Yuui Shimizu

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.

摘要翻译： 一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。

公开(公告)号：US20060279982A1

公开(公告)日：2006-12-14

申请号：US11217296

申请日：2005-09-02

申请人： Yuui Shimizu ,  Yoshihisa Iwata

发明人： Yuui Shimizu ,  Yoshihisa Iwata

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C5/025 ,  G11C5/063

摘要： A magnetic random access memory includes memory cells which store information using an internal magnetization direction. A first write line includes a first extending portion, a second extending portion and a first connection portion. The first extends portion extends along a first direction and has a first end and a second end. The second extending portion extends along the first direction and has a third end facing the first end and a fourth end facing the second end. The first connection portion connects the first end and the third end. A second write line and the first write line sandwiches one of the memory cells. First peripheral circuits are connected to the first connection portion and to at least one of the second end and the fourth end.

摘要翻译： 磁性随机存取存储器包括使用内部磁化方向存储信息的存储单元。 第一写入线包括第一延伸部分，第二延伸部分和第一连接部分。 第一延伸部分沿着第一方向延伸并且具有第一端部和第二端部。 第二延伸部分沿着第一方向延伸并且具有面向第一端的第三端和面向第二端的第四端。 第一连接部分连接第一端和第三端。 第二个写入行和第一个写入行夹在其中一个存储单元中。 第一外围电路连接到第一连接部分和第二端部和第四端部中的至少一个。

公开(公告)号：US07095649B2

公开(公告)日：2006-08-22

申请号：US10952721

申请日：2004-09-30

申请人： Yuui Shimizu ,  Kenji Tsuchida

发明人： Yuui Shimizu ,  Kenji Tsuchida

IPC分类号： G11C11/00

CPC分类号： G11C29/816 ,  G11C11/16 ,  G11C29/808

摘要： A semiconductor integrated circuit device includes a main memory cell array, redundant memory cell array, write current source, a common node connected to the write current source, a first selector connected between the common node and one-side ends of main write wirings and a second selector connected between the common node and one-side ends of redundant write wirings. The redundant memory cell array is arranged in a position apart from the main memory cell array and the write current source is commonly used by the main memory cell array and redundant memory cell array via the common node.

摘要翻译： 一种半导体集成电路装置，包括主存储单元阵列，冗余存储单元阵列，写入电流源，连接到写入电流源的公共节点，连接在公共节点和主要写入配线的一侧端部之间的第一选择器，以及 第二选择器连接在公共节点和冗余写配线的一端之间。 冗余存储单元阵列布置在远离主存储单元阵列的位置，并且写入电流源通过主存储单元阵列和冗余存储单元阵列经由公共节点共同使用。

公开(公告)号：US08730757B2

公开(公告)日：2014-05-20

申请号：US13602626

申请日：2012-09-04

申请人： Yuui Shimizu

发明人： Yuui Shimizu

IPC分类号： G11C8/00

CPC分类号： G11C16/32 ,  G11C7/1066 ,  G11C16/26 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

摘要： According to one embodiment, a memory system includes a first semiconductor memory and a controller. The first semiconductor memory receives a first clock, and outputs, in accordance with the first clock, a second clock and a data signal in synchronization with the second clock. The controller includes a detection circuit which detects a shift of a duty ratio of the second clock which is output from the first semiconductor memory. The controller also includes an adjustment circuit which adjusts a duty ratio of the first clock based on the shift detected by the detection circuit.

摘要翻译： 根据一个实施例，存储器系统包括第一半导体存储器和控制器。 第一半导体存储器接收第一时钟，并且根据第一时钟输出与第二时钟同步的第二时钟和数据信号。 控制器包括检测电路，其检测从第一半导体存储器输出的第二时钟的占空比的偏移。 控制器还包括调整电路，该调整电路根据由检测电路检测到的移位来调节第一时钟的占空比。

公开(公告)号：US08558576B2

公开(公告)日：2013-10-15

申请号：US13040762

申请日：2011-03-04

申请人： Yuui Shimizu

发明人： Yuui Shimizu

IPC分类号： H03K19/094 ,  H03B1/00

CPC分类号： H03K19/094

摘要： According to one embodiment, a clamp transistor is inserted in series between a P-channel field effect transistor and an N-channel field effect transistor and an intermediate level between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor is input into a gate of the clamp transistor to clamp a drain potential of the N-channel field effect transistor.

摘要翻译： 根据一个实施例，钳位晶体管串联插入在P沟道场效应晶体管和N沟道场效应晶体管之间，并且在提供给P沟道场效应晶体管的源极的高电位和 提供给N沟道场效应晶体管的源极的低电位被输入到钳位晶体管的栅极，以钳位N沟道场效应晶体管的漏极电位。