公开(公告)号：US07190611B2

公开(公告)日：2007-03-13

申请号：US10338148

申请日：2003-01-07

申请人： Paul P. Nguyen ,  Yiming Huai

发明人： Paul P. Nguyen ,  Yiming Huai

IPC分类号： G11C11/00 ,  H01L43/00

CPC分类号： G11C11/15 ,  G11C11/5607

摘要： A magnetic element for a high-density memory array includes a resettable layer and a storage layer. The resettable layer has a magnetization that is set in a selected direction by at least one externally generated magnetic field. The storage layer has at least one magnetic easy axis and a magnetization that changes direction based on the spin-transfer effect when a write current passes through the magnetic element. An alternative embodiment of the magnetic element includes an additional multilayer structure formed from a tunneling barrier layer, a pinned magnetic layer and an antiferromagnetic layer that pins the magnetization of the pinned layer in a predetermined direction. Another alternative embodiment of the magnetic element includes an additional multilayer structure that is formed from a tunneling barrier layer and a second resettable layer having a magnetic moment that is different from the magnetic moment of the resettable layer of the basic embodiment.

摘要翻译： 用于高密度存储器阵列的磁性元件包括可重置层和存储层。 可复位层具有通过至少一个外部产生的磁场在选定方向上设定的磁化。 当写入电流通过磁性元件时，存储层具有至少一个易磁化轴和基于自旋转移效应改变方向的磁化。 磁性元件的替代实施例包括由隧道势垒层，钉扎磁性层和反铁磁层形成的额外的多层结构，其在预定方向上钉住钉扎层的磁化。 磁性元件的另一替代实施例包括由隧道势垒层和具有与基本实施例的可重置层的磁矩不同的磁矩的第二可复位层形成的附加多层结构。

公开(公告)号：US07161829B2

公开(公告)日：2007-01-09

申请号：US10665945

申请日：2003-09-19

申请人： Yiming Huai ,  Paul P. Nguyen ,  Frank Albert

发明人： Yiming Huai ,  Paul P. Nguyen ,  Frank Albert

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/16

摘要： A method and system for providing and magnetic element is disclosed. In one aspect, the magnetic element includes at least a pinned layer, a free layer, and a current confined layer residing between the pinned layer and the free layer. The pinned layer is ferromagnetic and has a first magnetization. The current confined layer has at least one channel in an insulating matrix. The channel(s) are conductive and extend through the current confined layer. The free layer is ferromagnetic and has a second magnetization. The pinned layer, the free layer, and the current confined layer are configured to allow the magnetization of the free layer to be switched using spin transfer. The magnetic element may also include other layers, including layers for spin valve(s), spin tunneling junction(s), dual spin valve(s), dual spin tunneling junction(s), and dual spin valve/tunnel structure(s).

摘要翻译： 公开了一种用于提供和磁性元件的方法和系统。 在一个方面，磁性元件至少包括钉扎层，自由层和驻留在被钉扎层和自由层之间的电流限制层。 被钉扎层是铁磁性的并且具有第一磁化强度。 电流限制层在绝缘矩阵中具有至少一个通道。 通道是导电的并延伸通过电流限制层。 自由层是铁磁性的并且具有第二磁化强度。 被钉扎层，自由层和电流限制层被配置为允许使用自旋转移来切换自由层的磁化。 磁性元件还可以包括其它层，包括用于自旋阀的层，自旋隧道结，双自旋阀，双自旋隧道结，以及双自旋阀/隧道结构， 。

公开(公告)号：US07098494B2

公开(公告)日：2006-08-29

申请号：US10869734

申请日：2004-06-16

申请人： Mahendra Pakala ,  Yiming Huai

发明人： Mahendra Pakala ,  Yiming Huai

IPC分类号： H01L31/062

CPC分类号： H03K19/168 ,  B82Y25/00 ,  H01F10/3254 ,  H01L43/08

摘要： A magnetic logic cell includes a magnetic element having a pinned layer, a free layer, and a spacer layer. The pinned and free layers have pinned and free layer magnetizations. The spacer layer resides between the pinned and free layers. In one aspect, the magnetic logic cell includes a first configuration line that is electrically connected to the magnetic element and carries a first current and a second configuration line electrically that is insulated from the magnetic element and the first configuration line and carries a second current. The first or second current alone cannot switch the free layer magnetization. The first and second currents together can switch the free layer magnetization. When the first current is driven through the magnetic element and the second current is provided, the combination sets the pinned layer magnetization direction. In one aspect, the pinned layer magnetization is set by heating the AFM layer to approximately at or above the blocking temperature. In order to configure the logic cell, an initial direction for the free layer magnetization is also set.

摘要翻译： 磁逻辑单元包括具有钉扎层，自由层和间隔层的磁性元件。 被钉扎和自由层具有钉扎和自由层磁化。 间隔层位于固定层和自由层之间。 在一个方面，磁逻辑单元包括电连接到磁性元件的第一配置线，并且电连接第一电流和第二配置线，其与磁性元件和第一配置线绝缘并且承载第二电流。 单独的第一或第二电流不能切换自由层磁化。 第一和第二电流一起可以切换自由层的磁化。 当第一电流被驱动通过磁性元件并且提供第二电流时，组合设置钉扎层的磁化方向。 在一个方面，通过将AFM层加热到大约等于或高于阻挡温度来设定钉扎层的磁化强度。 为了配置逻辑单元，还设置了自由层磁化的初始方向。

公开(公告)号：US07009877B1

公开(公告)日：2006-03-07

申请号：US10714073

申请日：2003-11-14

申请人： Yiming Huai ,  Paul P. Nguyen ,  Frank Albert

发明人： Yiming Huai ,  Paul P. Nguyen ,  Frank Albert

IPC分类号： G11C11/14

CPC分类号： H01L27/228 ,  G11C11/16 ,  H01L43/08

摘要： A magnetic memory device for reading and writing a data state comprises at least three terminals including first, second, and third terminals. The magnetic memory device also includes a spin transfer (ST) driven element, disposed between the first terminal and the second terminal, and a readout element, disposed between the second terminal and the third terminal. The ST driven element includes a first free layer, and a readout element includes a second free layer. A magnetization direction of the second free layer in the readout element indicates a data state. A magnetization reversal of the first free layer within the ST driven element magnetostatically causes a magnetization reversal of the second free layer in the readout element, thereby recording the data state.

摘要翻译： 用于读取和写入数据状态的磁存储器件包括至少三个包括第一，第二和第三端子的端子。 磁存储装置还包括设置在第一端子和第二端子之间的自旋转移（ST）驱动元件和设置在第二端子和第三端子之间的读出元件。 ST驱动元件包括第一自由层，读出元件包括第二自由层。 读出元件中的第二自由层的磁化方向表示数据状态。 ST驱动元件内的第一自由层的磁化反转磁静态地导致读出元件中第二自由层的磁化反转，从而记录数据状态。

公开(公告)号：US06888742B1

公开(公告)日：2005-05-03

申请号：US10231430

申请日：2002-08-28

申请人： Paul P. Nguyen ,  Yiming Huai

发明人： Paul P. Nguyen ,  Yiming Huai

IPC分类号： G11C11/15 ,  G11C11/00

CPC分类号： G11C11/15

摘要： A method and system for providing a magnetic element capable of being written in a reduced time using the spin-transfer effect while generating a high output signal and a magnetic memory using the magnetic element are disclosed. The magnetic element includes a ferromagnetic pinned layer, a nonmagnetic intermediate layer, and a ferromagnetic free layer. The pinned layer has a magnetization pinned in a first direction. The nonmagnetic intermediate layer resides between the pinned layer and the free layer. The free layer has a magnetization with an easy axis in a second direction. The first direction is in the same plane as the second direction and is oriented at an angle with respect to the second direction. This angle is different from zero and π radians. The magnetic element is also configured to allow the magnetization of the free layer to change direction due to spin transfer when a write current is passed through the magnetic element.

摘要翻译： 公开了一种方法和系统，用于提供能够使用自旋转移效应以减少的时间写入的磁性元件，同时产生高输出信号和使用该磁性元件的磁性存储器。 磁性元件包括铁磁性钉扎层，非磁性中间层和铁磁性自由层。 钉扎层具有沿第一方向固定的磁化。 非磁性中间层位于被钉扎层和自由层之间。 自由层在第二方向上具有容易轴的磁化。 第一方向与第二方向在同一平面中，并且相对于第二方向成一定角度。 该角度与零和pi弧度不同。 磁性元件还被配置为当写入电流通过磁性元件时，由于自旋转移使自由层的磁化改变方向。

公开(公告)号：US08913350B2

公开(公告)日：2014-12-16

申请号：US12538489

申请日：2009-08-10

申请人： Steven M. Watts ,  Zhitao Diao ,  Xueti Tang

发明人： Steven M. Watts ,  Zhitao Diao ,  Xueti Tang

IPC分类号： G11B5/33 ,  B82Y40/00 ,  G11C11/16 ,  H01L43/08 ,  G01R33/09 ,  B82Y25/00 ,  H01F41/30 ,  H01F10/32 ,  H01F41/34

CPC分类号： G01R33/098 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/307 ,  H01F41/325 ,  H01F41/34 ,  H01L43/08

摘要： A method and system for providing a magnetic element and a magnetic memory utilizing the magnetic element are described. The magnetic element is used in a magnetic device that includes a contact electrically coupled to the magnetic element. The method and system include providing pinned, nonmagnetic spacer, and free layers. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The method and system also include providing a perpendicular capping layer adjoining the free layer and the contact. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy in the free layer. The magnetic element is configured to allow the free layer to be switched between magnetic states when a write current is passed through the magnetic element.

摘要翻译： 描述了一种用于提供使用磁性元件的磁性元件和磁性存储器的方法和系统。 磁性元件用于包括电耦合到磁性元件的触点的磁性装置中。 该方法和系统包括提供固定，非磁性间隔物和自由层。 自由层具有对应于小于面外去磁能的垂直各向异性能的平面退磁能和垂直磁各向异性。 非磁性间隔层位于被钉扎层和自由层之间。 该方法和系统还包括提供与自由层和接触相邻的垂直覆盖层。 垂直覆盖层在自由层中引起至少一部分垂直磁各向异性。 磁性元件被配置为当写入电流通过磁性元件时允许自由层在磁状态之间切换。

公开(公告)号：US20140032812A1

公开(公告)日：2014-01-30

申请号：US13444079

申请日：2012-04-11

申请人： Adrian E. Ong

发明人： Adrian E. Ong

IPC分类号： G11C7/22

CPC分类号： G11C7/222 ,  G11C7/1018 ,  G11C7/22 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0088

摘要： A non-volatile memory (NVM) system compatible with double data rate, single data rate, or other high speed serial burst operation. The NVM system includes input and output circuits adapted to synchronously send or receive back-to-back continuous bursts of serial data at twice the frequency of any clock input. Each burst is J bits in length. The NVM system includes read and write circuits that are adapted to read or write J bits of data at a time and in parallel, for each of a multitude of parallel data paths. Data is latched such that write time is similar for each bit and is extended to the time it takes to transmit an entire burst. Consequently, the need for small and fast sensing circuits on every column of a memory array, and fast write time at twice the frequency of the fastest clock input, are relieved.

摘要翻译： 兼容双数据速率，单数据速率或其他高速串行脉冲串操作的非易失性存储器（NVM）系统。 NVM系统包括适用于以任何时钟输入频率的两倍同步发送或接收串行数据的背靠背连续脉冲串的输入和输出电路。 每个突发是长度为J比特。 NVM系统包括用于针对多个并行数据路径中的每一个而并行地读取或写入J位数据的读取和写入电路。 数据被锁存，使得每个位的写入时间相似，并且扩展到发送整个脉冲串所需的时间。 因此，需要在存储器阵列的每一列上的小型和快速感测电路以及以最快时钟输入频率的两倍的快速写入时间。

公开(公告)号：US08315090B2

公开(公告)日：2012-11-20

申请号：US12903152

申请日：2010-10-12

申请人： Adrian E. Ong

发明人： Adrian E. Ong

IPC分类号： G11C11/14

CPC分类号： G11C13/0069 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0026 ,  G11C13/0061 ,  G11C16/0408 ,  G11C16/0466 ,  G11C2013/0088 ,  G11C2213/79 ,  Y10T29/49002

摘要： A non-volatile memory array includes a plurality of word-lines and a plurality of columns. One of the columns further includes a bistable regenerative circuit coupled to a first, a second, a third, and a fourth signal lines. The column also includes a non-volatile memory cell having current carrying terminals coupled to the first and second signal lines and a control terminal coupled to one of the plurality of word-lines. The column further includes a first transistor and a second transistor. The first transistor is coupled to the first terminal of the bistable regenerative circuit, and to a fifth signal line. The second transistor has a first current carrying terminal coupled to the second terminal of the bistable regenerative circuit, and a second current carrying terminal coupled to a sixth signal line. The gate terminals of the first and second transistors are coupled to a seventh signal line.

摘要翻译： 非易失性存储器阵列包括多个字线和多个列。 其中一列还包括耦合到第一，第二，第三和第四信号线的双稳态再生电路。 该列还包括具有耦合到第一和第二信号线的载流端子和耦合到多个字线之一的控制端子的非易失性存储单元。 该列还包括第一晶体管和第二晶体管。 第一晶体管耦合到双稳态再生电路的第一端子和第五信号线。 第二晶体管具有耦合到双稳态再生电路的第二端子的第一载流端子和耦合到第六信号线的第二载流端子。 第一和第二晶体管的栅极端子耦合到第七信号线。

公开(公告)号：US20120257448A1

公开(公告)日：2012-10-11

申请号：US13083854

申请日：2011-04-11

申请人： Adrian E. Ong

发明人： Adrian E. Ong

IPC分类号： G11C11/14 ,  G11C7/00

CPC分类号： G11C11/1675 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2029/0411

摘要： A write circuit is adapted to provide a same logical bit to each of a multitude of memory cells for storage. Each of the multitude of memory cells stores either the bit or a complement of the bit in response to the write circuit. A read circuit is adapted to receive the bits stored in the multitude of memory cells and to generate an output value defined by the stored bits in accordance with a predefined rule. The predefined rule may be characterized by a statistical mode of the bits stored in the plurality of memory cells. Storage errors in a minority of the multitude of memory cells may be ignored at the cost of lower memory density. The predefined rule may be characterized by a first weight assigned to bits 1 and a second weight assigned to bits 0.

摘要翻译： 写入电路适于向多个用于存储的存储器单元中的每一个提供相同的逻辑位。 多个存储器单元中的每一个都存储响应于写入电路的位或位的补码。 读取电路适于接收存储在多个存储器单元中的位，并且根据预定义的规则生成由存储的位定义的输出值。 可以通过存储在多个存储器单元中的位的统计模式来表征预定规则。 少量存储器单元中的存储错误可能以较低的存储器密度为代价而被忽略。 预定义规则可以由分配给比特1的第一权重和分配给比特0的第二权重来表征。

公开(公告)号：US20120246507A1

公开(公告)日：2012-09-27

申请号：US13427465

申请日：2012-03-22

申请人： Xiao Luo ,  Adrian E. Ong

发明人： Xiao Luo ,  Adrian E. Ong

IPC分类号： G06F11/07

CPC分类号： G06F11/1048

摘要： A system implementing parallel memory error detection and correction divides data having a word length of K bits into multiple N-bit portions. The system has a separate error processing subsystem for each of the N-bit portions, and utilizes each error processing subsystem to process the associated N-bit portion of the K-bit input data. During memory write operations, each error processing subsystem generates parity information for the N-bit data, and writes the N-bit data and parity information into a separate memory array that corresponds to the error processing subsystem. During memory read operations, each error processing subsystem reads N-bits of data and the associated parity information. If, based on the parity information, an error is detected from the N-bit data, the error processing subsystem attempts to correct the error. The corrected N-bit data from each of the error processing subsystems are combined to reproduce the K-bit word.

摘要翻译： 实现并行存储器错误检测和校正的系统将具有K位字长的数据分成多个N位部分。 该系统具有用于每个N位部分的单独的错误处理子系统，并利用每个错误处理子系统处理K位输入数据的相关联的N位部分。 在存储器写入操作期间，每个错误处理子系统产生N位数据的奇偶校验信息，并将N位数据和奇偶校验信息写入到对应于错误处理子系统的单独的存储器阵列中。 在存储器读取操作期间，每个错误处理子系统读取数据的N位和相关的奇偶校验信息。 如果基于奇偶校验信息从N位数据检测到错误，则错误处理子系统尝试校正错误。 来自每个错误处理子系统的经校正的N位数据被组合以再现K位字。