公开(公告)号：US20210281497A1

公开(公告)日：2021-09-09

申请号：US17182914

申请日：2021-02-23

Applicant: STMicroelectronics Application GMBH

Inventor： Fred Rennig

IPC: H04L12/26

Abstract: In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.

公开(公告)号：US11032067B2

公开(公告)日：2021-06-08

申请号：US16022110

申请日：2018-06-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

Inventor： Roberto Colombo ,  Guido Marco Bertoni ,  William Orlando ,  Roberta Vittimani

IPC: H04L9/08 ,  G06F13/36 ,  H04L9/14 ,  H04L9/32

Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.

公开(公告)号：US10949570B2

公开(公告)日：2021-03-16

申请号：US16039103

申请日：2018-07-18

Applicant: STMicroelectronics Application GmbH

Inventor： Roberto Colombo

IPC: G06F21/71 ,  G06F21/44 ,  G06F21/62 ,  G06F21/79

Abstract: In an embodiment, a processing system includes a non-volatile memory, a hardware block, a protection circuit associated with the hardware block, and a password verification circuit. The non-volatile memory stores at least one reference password. The password verification circuit is configured to receive a password verification command, obtain a reference password, and test whether the passwords correspond. In case the passwords correspond, the password verification circuit generate an overwrite signal. The protection circuit is configured to receive a control command and selectively forward the control command to the associated hardware block as a function of the overwrite signal.

公开(公告)号：US12117949B2

公开(公告)日：2024-10-15

申请号：US18364786

申请日：2023-08-03

Applicant: STMicroelectronics Application GMBH

Inventor： Rolf Nandlinger ,  Roberto Colombo

IPC: G06F13/28 ,  G06F9/30 ,  G06F9/38 ,  G06F13/42 ,  G06F21/60 ,  G06F21/72

CPC classification number: G06F13/28 ,  G06F9/30105 ,  G06F9/3877 ,  G06F13/4282 ,  G06F21/602 ,  G06F21/72

Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

公开(公告)号：US12047198B2

公开(公告)日：2024-07-23

申请号：US18320764

申请日：2023-05-19

Applicant: STMICROELECTRONICS APPLICATION GMBH

Inventor： Fred Rennig ,  Rolf Nandlinger

IPC: H04L12/40 ,  G06F13/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/4022 ,  G06F13/426 ,  H04L12/40169 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: A device has a plurality of CAN XL communication systems, a bus, and a switching circuit. The bus has a transmission node and reception node, and receives from each CAN XL communication system a respective second transmission signal and drives the logic level at the transmission node as a function of the logic levels of the second transmission signals, and provides to each CAN XL communication system a respective second reception signal having a logic level determined as a function of the logic level at the reception node. The switching circuit supports a plurality of modes. In a first mode, the switching circuit is configured to provide the NRZ encoded transmission signals of the CAN XL communication systems as the second transmission signals to the bus system, and provide the respective second reception signal received from the bus to the CAN XL protocol controllers of the CAN XL communication system.

公开(公告)号：US11973457B2

公开(公告)日：2024-04-30

申请号：US17323602

申请日：2021-05-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH ,  STMicroelectronics (Alps) SAS

Inventor： Aldo Occhipinti ,  Christophe Roussel ,  Fritz Burkhardt ,  Ignazio Testoni

IPC: H02P3/18 ,  E05F15/60 ,  H02P6/16 ,  H02P7/03 ,  H02P7/29 ,  H03K3/037 ,  H03K17/687 ,  B60J5/10 ,  B60R16/033

CPC classification number: H02P7/04 ,  E05F15/60 ,  H02P7/29 ,  H03K3/0377 ,  H03K17/6871 ,  B60J5/10 ,  B60R16/033 ,  E05Y2201/434 ,  E05Y2900/548 ,  H03K2217/0063 ,  H03K2217/0072 ,  H03K2217/0081

Abstract: An embodiment driver circuit comprises a power supply pin configured to receive a power supply voltage, and a set of control pins configured to provide a set of control signals for controlling switching of a set of switches of an h-bridge circuit comprising a pair of high-side switches and a pair of low-side switches. The driver circuit comprises control circuitry coupled to the control pins and configured to generate the control signals, and sensing circuitry coupled to the power supply pin and configured to generate a detection signal indicative of the power supply voltage exceeding a threshold value. The control circuitry is sensitive to the detection signal and is configured to generate the control signals to activate one of the pair of high-side switches and the pair of low-side switches and de-activate the other of the pair of high-side switches and the pair of low-side switches.

公开(公告)号：US11915008B2

公开(公告)日：2024-02-27

申请号：US17654537

申请日：2022-03-11

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Rene Grossier ,  Fabio Enrico Carlo Disegni

IPC: G06F9/44 ,  G06F9/4401 ,  G06F9/30

CPC classification number: G06F9/4403 ,  G06F9/30101

Abstract: In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.

公开(公告)号：US11822934B2

公开(公告)日：2023-11-21

申请号：US17341054

申请日：2021-06-07

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Roberto Colombo ,  Om Ranjan

IPC: G06F11/10 ,  G06F9/445 ,  G06F13/36 ,  H04L9/06 ,  H04L9/32

CPC classification number: G06F9/44505 ,  G06F11/1004 ,  G06F13/36 ,  H04L9/0643 ,  H04L9/3247

Abstract: A processing system includes a plurality of configuration data clients; each associated with a respective address and including a respective register, a hardware block, a non-volatile memory, and a hardware configuration circuit. A respective configuration data client receives a respective first configuration data and stores it in the respective register. The hardware block is coupled to at least one of the configuration data clients and changes operation as a function of the respective first configuration data stored in the respective registers. The non-volatile memory includes second configuration data stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients. The hardware configuration circuit sequentially reads the data packets from the non-volatile memory and transmits the respective first configuration data to the respective configuration data client.

公开(公告)号：US11764807B2

公开(公告)日：2023-09-19

申请号：US17858782

申请日：2022-07-06

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics International N.V.

Inventor： Vivek Mohan Sharma ,  Roberto Colombo

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1105 ,  H03M13/611

Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits. For example the safety monitor circuit comprises a test circuit configured to provide modified data bits and/or modified ECC bits to the error detection circuit as a function of connectivity test control signals, whereby the error detection circuit asserts the error signal as a function of the connectivity test control signals. The processing system comprises also a connectivity test control circuit comprising control registers programmable via the microprocessor, wherein the connectivity test control signals are generated as a function of the content of the control registers.

公开(公告)号：US20230267087A1

公开(公告)日：2023-08-24

申请号：US18309103

申请日：2023-04-28

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042 ,  G06F9/54

CPC classification number: G06F13/362 ,  G06F13/4068 ,  G06F11/0772 ,  G06F11/0739 ,  H04L12/403 ,  G06F11/0757 ,  G05B19/042 ,  G06F9/542 ,  H03M13/09

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.