公开(公告)号：US20140019717A1

公开(公告)日：2014-01-16

申请号：US14026469

申请日：2013-09-13

申请人： FUJITSU LIMITED

发明人： Koichiro Yamashita ,  Hiromasa Yamauchi ,  Takahisa Suzuki ,  Koji Kurihara

IPC分类号： G06F15/78

CPC分类号： G06F15/7839 ,  G06F8/458 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3885 ,  G06F9/467 ,  G06F9/52 ,  G06F9/544 ,  G06F15/167 ,  G06F2212/507

摘要： A synchronization method is executed by a multi-core processor system. The synchronization method includes registering based on a synchronous command issued from a first CPU, CPUs to be synchronized and a count of the CPUs into a specific table; counting by each of the CPUs and based on a synchronous signal from the first CPU, an arrival count for a synchronous point, and creating by each of the CPUs, a second shared memory area that is a duplication of a first shared memory area accessed by processes executed by the CPUs; and comparing the first shared memory area and the second shared memory area when the arrival count becomes equal to the count of the CPUs, and based on a result of the comparison, judging the processes executed by the CPUs.

摘要翻译： 同步方法由多核处理器系统执行。 同步方法包括基于从第一CPU发出的同步命令，要同步的CPU和CPU的计数到特定表中进行注册; 由每个CPU进行计数，并且基于来自第一CPU的同步信号，同步点的到达计数以及由每个CPU创建作为第一共享存储器区域的复制的第二共享存储区域 由CPU执行的进程; 以及当到达计数等于CPU的计数时，比较第一共享存储区域和第二共享存储区域，并且基于比较结果，判断由CPU执行的处理。

公开(公告)号：US08595465B1

公开(公告)日：2013-11-26

申请号：US12877788

申请日：2010-09-08

申请人： Moshe Raz

发明人： Moshe Raz

IPC分类号： G06F12/00 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F12/1027 ,  G06F2212/507

摘要： Some of the embodiments of the present disclosure provide a method for predicting, for a first virtual address, a first descriptor based at least in part on the one or more past descriptors associated with one or more past virtual addresses; and determining, for the first virtual address, a first physical address based at least in part on the predicted first descriptor. Other embodiments are also described and claimed.

摘要翻译： 本公开的一些实施例提供了一种用于至少部分地基于与一个或多个过去虚拟地址相关联的一个或多个过去描述符来为第一虚拟地址预测第一描述符的方法; 以及至少部分地基于所述预测的第一描述符，为所述第一虚拟地址确定第一物理地址。 还描述和要求保护其他实施例。

公开(公告)号：US08407432B2

公开(公告)日：2013-03-26

申请号：US11173917

申请日：2005-06-30

申请人： Zhong-Ning Cai ,  Krishnakanth V. Sistla ,  Yen-Cheng Liu ,  Jeffrey D. Gilbert

发明人： Zhong-Ning Cai ,  Krishnakanth V. Sistla ,  Yen-Cheng Liu ,  Jeffrey D. Gilbert

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0817 ,  G06F2212/507

摘要： A method and apparatus for cache coherency sequencing implementation and an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level cache access priority among multiple internal CMP cores, internal snoops and external snoops. Another embodiment provides mechanisms for implementing cache coherency in multi-core CMP system.

摘要翻译： 公开了一种用于高速缓存一致性排序实现和自适应LLC访问优先级控制的方法和装置。 一个实施例提供了解决多个内部CMP核心，内部窥探和外部窥探之间的最后一级高速缓存访​​问优先级的机制。 另一实施例提供了用于在多核CMP系统中实现高速缓存一致性的机制。

公开(公告)号：US08301843B2

公开(公告)日：2012-10-30

申请号：US12650075

申请日：2009-12-30

申请人： Ramesh Gunna ,  Sudarshan Kadambi ,  Peter J. Bannon

发明人： Ramesh Gunna ,  Sudarshan Kadambi ,  Peter J. Bannon

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0808 ,  G06F9/30047 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/0815 ,  G06F2212/507

摘要： In one embodiment, a processor comprises a core configured to execute a data cache block write instruction and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate. The core is configured to transmit a request to the interface unit in response to the data cache block write instruction. If the request is speculative, the interface unit is configured to issue a first transaction on the interconnect. On the other hand, if the request is non-speculative, the interface unit is configured to issue a second transaction on the interconnect. The second transaction is different from the first transaction. For example, the second transaction may be an invalidate transaction and the first transaction may be a probe transaction. In some embodiments, the processor may be in a system including the interconnect and one or more caching agents.

摘要翻译： 在一个实施例中，处理器包括被配置为执行数据高速缓存块写入指令的核心和耦合到所述核心和所述处理器被配置为在其上进行通信的互连的接口单元。 核心被配置为响应于数据高速缓存块写入指令向接口单元发送请求。 如果请求是推测性的，则接口单元被配置为在互连上发布第一事务。 另一方面，如果请求是非推测性的，则接口单元被配置为在互连上发布第二事务。 第二个交易与第一笔交易不同。 例如，第二事务可以是无效事务，并且第一事务可以是探查事务。 在一些实施例中，处理器可以在包括互连和一个或多个高速缓存代理的系统中。

公开(公告)号：US08255638B2

公开(公告)日：2012-08-28

申请号：US12113262

申请日：2008-05-01

申请人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

发明人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0822 ,  G06F12/0831 ,  G06F2212/507 ,  Y02D10/13

摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports, each port snoop filter implementing one or more parallel operating sub-filter elements that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.

摘要翻译： 一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与之可操作地相连的一个或多个本地高速缓冲存储器。 该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于从多处理器计算环境中的专用存储器写入源接收窥探请求。 每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，每个端口窥探滤波器实现一个或多个并行操作子滤波器元件，其适于同时滤除从相应专用存储器接收的窥探请求 写入源并将这些请求的子集转发到其相关联的处理单元。

公开(公告)号：US08190821B2

公开(公告)日：2012-05-29

申请号：US12250728

申请日：2008-10-14

申请人： Shinichi Iwasaki

发明人： Shinichi Iwasaki

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0884 ,  G06F12/0822 ,  G06F12/0862 ,  G06F2212/507

摘要： A cache control apparatus determines whether to adopt or not data acquired by a speculative fetch by monitoring a status of the speculative fetch which is a memory fetch request output before it becomes clear whether data requested by a CPU is stored in a cache of the CPU and time period obtained by adding up the time period from when the speculative fetch is output to when the speculative fetch reaches a memory controller and time period from completion of writing of data to a memory which is specified by a data write command that has been issued, before issuance of the speculative fetch, for the same address as that for which the speculative fetch is issued to when a response of the data write command is returned.

摘要翻译： 高速缓存控制装置在清除CPU所请求的数据是否存储在CPU的高速缓存中之前，通过监视作为存储器取出请求输出的推测提取的状态来确定是否采用通过推测获取获得的数据，以及 通过将推测推送输出到推测提取到达存储器控制器的时间段与从写入数据完成到由存储器发出的数据写入命令指定的存储器的时间段相加而获得的时间段， 在发出推测性提取之前，与返回数据写入命令的响应时相同的地址与发出推测性提取的地址相同。

公开(公告)号：US20120079208A1

公开(公告)日：2012-03-29

申请号：US12892476

申请日：2010-09-28

申请人： Simon C. Steely, JR. ,  William C. Hasenplaugh

发明人： Simon C. Steely, JR. ,  William C. Hasenplaugh

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0815 ,  G06F2212/507

摘要： An apparatus to resolve cache coherency is presented. In one embodiment, the apparatus includes a microprocessor comprising one or more processing cores. The apparatus also includes a probe speculative address file unit, coupled to a cache memory, comprising a plurality of entries. Each entry includes a timer and a tag associated with a memory line. The apparatus further includes control logic to determine whether to service an incoming probe based at least in part on a timer value.

摘要翻译： 提出了一种解决高速缓存一致性的设备。 在一个实施例中，该装置包括具有一个或多个处理核心的微处理器。 该装置还包括耦合到高速缓冲存储器的探测推测地址文件单元，包括多个条目。 每个条目包括定时器和与存储器线相关联的标签。 该装置还包括至少部分地基于定时器值来确定是否对入站探测器进行服务的控制逻辑。

公开(公告)号：US08135917B2

公开(公告)日：2012-03-13

申请号：US12137325

申请日：2008-06-11

申请人： Matthias A. Blumrich ,  Alan G. Gara ,  Valentina Salapura

发明人： Matthias A. Blumrich ,  Alan G. Gara ,  Valentina Salapura

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0831 ,  G06F12/0822 ,  G06F2212/507 ,  Y02D10/13

摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having a local cache memory associated therewith. A snoop filter device is associated with each processing unit and includes at least one snoop filter primitive implementing filtering method based on usage of stream registers sets and associated stream register comparison logic. From the plurality of stream registers sets, at least one stream register set is active, and at least one stream register set is labeled historic at any point in time. In addition, the snoop filter block is operatively coupled with cache wrap detection logic whereby the content of the active stream register set is switched into a historic stream register set upon the cache wrap condition detection, and the content of at least one active stream register set is reset. Each filter primitive implements stream register comparison logic that determines whether a received snoop request is to be forwarded to the processor or discarded.

摘要翻译： 一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联的本地高速缓冲存储器。 窥探过滤设备与每个处理单元相关联并且包括至少一个基于流寄存器集合和相关流寄存器比较逻辑的使用实现过滤方法的窥探过滤器原语。 从多个流寄存器组中，至少一个流寄存器组是有效的，并且至少一个流寄存器集合在任何时间点被标记为历史。 另外，监听滤波器块可操作地与高速缓存包检测逻辑耦合，从而将活动流寄存器集合的内容切换到在高速缓存环绕条件检测时设置的历史流寄存器，并且至少一个活动流寄存器集合的内容 被复位。 每个滤波器基元实现流寄存器比较逻辑，其确定接收的窥探请求是否被转发到处理器或丢弃。

公开(公告)号：US08108616B2

公开(公告)日：2012-01-31

申请号：US12424829

申请日：2009-04-16

申请人： Ahmed M. Gheith

发明人： Ahmed M. Gheith

IPC分类号： G06F12/00

CPC分类号： G06F9/383 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/3851 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/507 ,  G06F2212/6026

摘要： Disclosed are a method, a system, and a program product for processing a data stream by accessing one or more hardware registers of a processor. In one or more embodiments, a first program instruction or subroutine can associate a hardware register of the processor with a data stream. With this association, the hardware register can be used as a stream head which can be used by multiple program instructions to access the data stream. In one or more embodiments, data from the data stream can be fetched automatically as needed and with one or more patterns which may include one or more start positions, one or more lengths, one or more strides, etc. to allow the cache to be populated with sufficient amounts of data to reduce memory latency and/or external memory bandwidth when executing an application which accesses the data stream through the one or more registers.

摘要翻译： 公开了一种通过访问处理器的一个或多个硬件寄存器来处理数据流的方法，系统和程序产品。 在一个或多个实施例中，第一程序指令或子程序可将处理器的硬件寄存器与数据流相关联。 通过该关联，硬件寄存器可以被用作可以被多个程序指令用于访问数据流的流头。 在一个或多个实施例中，可以根据需要自动获取来自数据流的数据，并且可以使用一个或多个模式，其可以包括一个或多个开始位置，一个或多个长度，一个或多个步骤等，以允许高速缓存为 在执行通过一个或多个寄存器访问数据流的应用程序时，填充足够数量的数据以减少存储器延迟和/或外部存储器带宽。

公开(公告)号：US20110320743A1

公开(公告)日：2011-12-29

申请号：US12822331

申请日：2010-06-24

申请人： Norbert Hagspiel ,  Matthias Klein ,  Ulrich Mayer ,  Robert J. Sonnelitter, III ,  Gary E. Strait ,  Hanno Ulrich

发明人： Norbert Hagspiel ,  Matthias Klein ,  Ulrich Mayer ,  Robert J. Sonnelitter, III ,  Gary E. Strait ,  Hanno Ulrich

IPC分类号： G06F12/00

CPC分类号： G06F12/0815 ,  G06F9/3842 ,  G06F9/528 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/1054 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/621

摘要： A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.

摘要翻译： 提供了一种用于以快速的顺序将数据存储在计算机系统的存储器中的系统和计算机实现的方法。 该方法包括向存储器启动第一个存储。 启动等待计数器。 当等待计数器到期时，第二家存储器被推测启动。 当第二个存储在第一个存储到存储器之前实现相关性时，第二个存储器的存储被取消。