公开(公告)号：US5550865A

公开(公告)日：1996-08-27

申请号：US287194

申请日：1994-08-08

申请人： Peter K. Cripps

发明人： Peter K. Cripps

IPC分类号： H03C3/09 ,  H04B1/40 ,  H04L25/49 ,  H04L27/12 ,  H04L27/148 ,  H04L27/04

CPC分类号： H03C3/0975 ,  H04B1/40 ,  H04L25/4925 ,  H04L27/12 ,  H04L27/148

摘要： A full duplex data transceiver for transmitting and receiving trinary frequency-modulated ("FM") signals representing binary data includes separate transmit and receive antennas, and a single oscillator which serves as both the radio frequency ("RF") signal source for the transmitter and the local oscillator "LO") signal source for the receiver. During signal transmission, the oscillator output is frequency-modulated to provide a FM transmit signal to the transmit antenna. The oscillator output is frequency-modulated with binary transmit data by modulating an error feedback signal which serves as the control voltage for a voltage-controlled oscillator in a phase-lock-loop, thereby producing the FM transmit signal. During signal reception, the oscillator output, in the form of the transmitted FM signal, is received via the receive antenna along with a FM receive signal for mixing therewith to down-convert the FM receive signal. As part of the demodulation of the down-converted FM receive signal, the binary transmit data is subtracted out. The FM transmit and receive signals are trinary (f.sub.-P, f.sub.c, f.sub.+P) and represent encoded binary data. The center frequency f.sub.c corresponds to an absence of a binary data signal transition, the lower peak frequency f.sub.-P corresponds to a negative binary data signal transition and the upper peak frequency f.sub.+P corresponds to a positive binary data signal transition.

摘要翻译： 用于发送和接收代表二进制数据的三进制调频（“FM”）信号的全双工数据收发器包括单独的发射和接收天线，以及用作发射机的射频（“RF”）信号源的单个振荡器 和本地振荡器“LO”）信号源。 在信号传输期间，振荡器输出被调频以向发射天线提供FM发射信号。 振荡器输出通过调制作为锁相环中的压控振荡器的控制电压的误差反馈信号进行二进制发送数据的频率调制，从而产生FM发送信号。 在信号接收期间，经发送的FM信号形式的振荡器输出与FM接收信号一起经FM接收信号接收，以便与FM接收信号下变频。 作为对下变频FM接收信号的解调的一部分，二进制发送数据被减去。 FM发送和接收信号是三进制（f-P，fc，f + P），并表示编码的二进制数据。 中心频率fc对应于二进制数据信号转换的缺失，较低的峰值频率f-P对应于负的二进制数据信号转换，而上峰值频率f + P对应于正的二进制数据信号转换。

公开(公告)号：US5313173A

公开(公告)日：1994-05-17

申请号：US51875

申请日：1993-04-26

申请人： Ross W. Lampe

发明人： Ross W. Lampe

IPC分类号： H03C3/09 ,  H03L7/16 ,  H03L7/22 ,  H03C3/00 ,  H03L7/081

CPC分类号： H03C3/0983 ,  H03C3/095 ,  H03C3/0975 ,  H03L7/16 ,  H03L7/22

摘要： A phase-locked loop incorporates a quadrature modulator for generating constant envelope phase or frequency modulation. Locating the quadrature modulator within the feedback loop or feeding the output signal of the quadrature modulator into the feedback loop permits accurate constant envelope phase modulation of the loop reference oscillator and completely suppresses undesired AM and PM components of the modulated signal.

摘要翻译： 锁相环包括用于产生恒定包络相位或频率调制的正交调制器。 在反馈环路内定位正交调制器或将正交调制器的输出信号馈送到反馈环路允许环路参考振荡器的精确恒定包络相位调制，并完全抑制调制信号的不需要的AM和PM分量。

公开(公告)号：US4918405A

公开(公告)日：1990-04-17

申请号：US263081

申请日：1988-10-26

申请人： Earl C. Herleikson

发明人： Earl C. Herleikson

IPC分类号： H03L7/187 ,  H03C3/00 ,  H03C3/09 ,  H03L7/113 ,  H03L7/18 ,  H03L7/189 ,  H03L7/197

CPC分类号： H03C3/0975 ,  H03C3/0925 ,  H03C3/0941 ,  H03L7/113 ,  H03L7/189 ,  H03L7/197

摘要： A programmable low noise frequency modulated signal source including a voltage controlled oscillator (VCO) having a frequency locked loop (FLL) constituting a first feedback path and a phase lock loop (PLL) constituting a second feedback path is provided. The PLL includes a VCO, a programmable fractional-N frequency division network for changing the rational number by which the VCO output signal is frequency divided, a phase detector for comparing the phase of the VCO output signal with the phase of a reference signal and for producing an error signal for controllably adjusting the output frequency of the VCO. The FLL includes a delay line frequency discriminator, a loop amplifier and filter to provide a first feedback signal to the VCO to thereby reduce the phase noise on the VCO output signal. The frequency discriminator includes a first signal path having a frequency sensitive time delay network to provide a phase shift as a function of the VCO output signal frequency and a second signal path which includes a voltage controlled phase shifting network. The VCO tune voltage derived from the PLL phase detector is coupled to an input terminal at the voltage controlled phase shifting network. The tune voltage adjusts the phase difference between the two frequency discriminator signal paths to set the operating point of the FLL phase detector such that the VCO output signal will have a desired frequency. Since the PLL VCO tune signal is coupled to the control input of the voltage control phase shifting network the FLL phase detector operates without an offset voltage at its output. Low distortion frequency modulation of the (FM) VCO output signal is achieved by coupling an FM signal to the voltage controlled variable phase shift network.

公开(公告)号：US4706047A

公开(公告)日：1987-11-10

申请号：US936528

申请日：1986-12-01

申请人： Louis J. Avila ,  John E. Merritt ,  Norman G. Hempling

发明人： Louis J. Avila ,  John E. Merritt ,  Norman G. Hempling

IPC分类号： H03C3/00 ,  H03C3/09

CPC分类号： H03C3/0975 ,  H03C3/00 ,  H03C3/0941 ,  H03C3/0966

摘要： A circuit for extending the frequency range of a digitally generated FM signal (f). A digital frequency generator (1) generates a precise FM waveform at a frequency up to about 50 MHz. Coupled to the FM signal (f) is a phase lock loop (53, 55, 57) comprising a voltage controlled oscillator (VCO) (57) whose output frequency can be much higher than the frequency of the FM signal (f). In a first embodiment, a crystal oscillator (61), mixer (59), and low pass filter (63) are used to bring the output (f') of the VCO (57) down into the range of the digital frequency generator (1). In a second embodiment, an analog frequency divider (73) is used to bring the output (f') of the VCO (57) into the range of the digital frequency generator (1). In a third embodiment, the single sideband (SSB) generator (37) from the digital frequency generator (1) and a counter (66) are used in a partly analog, partly digital, negative feedback loop.

摘要翻译： 一种用于扩展数字产生的FM信号（f）的频率范围的电路。 数字频率发生器（1）以高达约50MHz的频率产生精确的FM波形。 耦合到FM信号（f）的是锁相环（53,55,57），其包括压控振荡器（VCO）（57），其输出频率可以比FM信号（f）的频率高得多。 在第一实施例中，使用晶体振荡器（61），混频器（59）和低通滤波器（63）将VCO（57）的输出（f'）降低到数字频率发生器 1）。 在第二实施例中，使用模拟分频器（73）使VCO（57）的输出（f'）进入数字频率发生器（1）的范围。 在第三实施例中，来自数字频率发生器（1）的单边带（SSB）发生器（37）和计数器（66）用于部分模拟部分数字负反馈环路。

公开(公告)号：US4492936A

公开(公告)日：1985-01-08

申请号：US408874

申请日：1982-08-17

申请人： Alain Albarello ,  Andre Roullet ,  Alberto Pimentel

发明人： Alain Albarello ,  Andre Roullet ,  Alberto Pimentel

IPC分类号： H03L7/18 ,  H03C3/09 ,  H03L7/183 ,  H03L7/197 ,  H04L27/12 ,  H03C3/06 ,  H04B1/04

CPC分类号： H03C3/0975 ,  H03C3/0925 ,  H03C3/0941 ,  H03L7/1976 ,  H04L27/12 ,  H03C2200/0029

摘要： In order to deliver an angle-modulated output signal as a function of digital information, the frequency synthesizer delivers an output frequency F.sub.S =(N+k)F.sub.R, where N is the integral part of a number N+k and F.sub.R is a reference frequency. Provision is made for a variable oscillator, an oscillator control loop comprising in series a variable divider having a preselected divisor N, a phase comparator for receiving the reference frequency and a summing device. The synthesizer further comprises a phase accumulator for performing, at the frequency F.sub.R, modulo-M summation of a number G=k(M) applied to its input. The sum and carry outputs of the accumulator are coupled respectively to the summing device in order to deliver a signal for compensating the signal delivered by the phase comparator and to the divider for delivering a control signal to select the divisor N+1. An adder having one output coupled to the input of the phase accumulator receives a constant number g on one input and a number dg which is representative of the digital information on another input.

摘要翻译： 为了提供作为数字信息的函数的角度调制输出信号，频率合成器输出输出频率FS =（N + k）FR，其中N是数字N + k的整数部分，FR是参考 频率。 提供了一种可变振荡器，一个振荡器控制回路，其串联包括具有预选除数N的可变分频器，用于接收参考频率的相位比较器和一个求和装置。 合成器还包括相位累加器，用于以频率FR执行施加到其输入的数G = k（M）的模M求和。 累加器的和和进位输出分别耦合到求和装置，以便传送用于补偿由相位比较器传递的信号的信号和分配器，用于传送控制信号以选择除数N + 1。 具有耦合到相位累加器的输入的一个输出的加法器在一个输入端上接收恒定数量g，并且代表代表关于另一个输入的数字信息的数字dg。

公开(公告)号：US20170207807A1

公开(公告)日：2017-07-20

申请号：US15478968

申请日：2017-04-04

申请人： SAMSUNG ELECTRONICS CO., LTD. ,  Sungkyunkwan University Foundation for Corporate Collaboration

发明人： Jaesup LEE ,  Hong Jin KIM ,  Hyung Gu PARK ,  Kang Yoon LEE

IPC分类号： H04B1/38 ,  H04L5/00 ,  H03L7/08 ,  H04L7/033 ,  H03B5/12 ,  H03L7/099

CPC分类号： H04B1/38 ,  H03B5/1215 ,  H03B5/1228 ,  H03B2200/0062 ,  H03C3/0916 ,  H03C3/0975 ,  H03C3/0991 ,  H03L7/0802 ,  H03L7/0895 ,  H03L7/0898 ,  H03L7/099 ,  H03L7/1072 ,  H04L5/0062 ,  H04L7/033 ,  H04L2027/0016 ,  H04L2027/0022 ,  H04L2027/0055

摘要： A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part. The PLL may be controlled according to whether the reception RF part or the transmission RF part is on. In addition, a transceiver may include quenching waveform generator (QWGs) to control quenching waveforms of the RF parts corresponding to a plurality of antennas. The quenching waveforms may be generated respectively by VCOs operating at a same frequency. The QWGs may control the VCOs such that the quenching waveforms do not overlap.

公开(公告)号：US20160191284A1

公开(公告)日：2016-06-30

申请号：US14969524

申请日：2015-12-15

申请人： Yasuhiro IZAWA

发明人： Yasuhiro IZAWA

IPC分类号： H04L27/20 ,  H04B1/04 ,  H04L27/00

CPC分类号： H04B1/0475 ,  H03C3/0916 ,  H03C3/0975 ,  H03L7/18 ,  H04B15/04

摘要： A clock signal generating apparatus detects a phase difference between an input reference clock signal and a feedback signal to output a control signal based on the phase difference, generates the clock signal with a frequency based on the output control signal, generates a pattern by switching, at a certain time interval, between a plurality of patterns of a second phase shift amount, adds a first phase shift amount to the second phase shift amount having the generated pattern, determines a phase to be selected, so that a cycle of the phase-shifted clock signal matches the cycle of a clock signal changed by the first phase shift amount to which the second phase shift amount is added, selects the determined phase from among a plurality of phases, and generates a phase-shifted clock signal whose signal level changes in the selected phase for output as the feedback signal.

摘要翻译： 时钟信号发生装置检测输入基准时钟信号和反馈信号之间的相位差，以基于相位差输出控制信号，根据输出控制信号产生具有频率的时钟信号，通过切换产生模式， 在一定的时间间隔，在第二相移量的多个图案之间，将具有所产生的图案的第二相移量的第一相移量相加，确定要选择的相位， 移位的时钟信号与被添加了第二相移量的第一相移量改变的时钟信号的周期匹配，从多个相位中选择确定的相位，并产生信号电平变化的相移时钟信号 在选择的相位作为反馈信号输出。

公开(公告)号：US20150229317A1

公开(公告)日：2015-08-13

申请号：US14616192

申请日：2015-02-06

申请人： DUST NETWORKS, INC.

发明人： Thor Nelson JUNEAU ,  Mark Alan LEMKIN

IPC分类号： H03L7/18

CPC分类号： H03L7/18 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0966 ,  H03C3/0975 ,  H03K3/0315 ,  H03L7/0814

摘要： A frequency synthesizer directly generates phase modulated radio-frequency (RF) signals. The frequency synthesizer includes a voltage controlled oscillator (VCO) producing a synthesized frequency signal having a frequency controlled based on a signal received at an input of the VCO. A digitally adjustable frequency divider produces a reduced frequency signal from the synthesized frequency signal. A phase digital-to-analog converter (DAC) produces a delayed version of a timing signal (e.g., the reduced frequency signal, or a reference clock signal) that is delayed according to a digital control signal. A phase detector (PD) produces a phase control signal from the reduced frequency signal and/or the delayed timing signal. A digital signal converter controls the digitally adjustable frequency divider and the phase DAC so as to cause a phase or frequency of the synthesized frequency signal output by the VCO to track a desired phase or frequency trajectory encoded in a digital signal.

摘要翻译： 频率合成器直接产生相位调制的射频（RF）信号。 频率合成器包括压控振荡器（VCO），其产生具有基于在VCO的输入处接收的信号的频率控制的合成频率信号。 数字可调分频器产生来自合成频率信号的降频信号。 相位数/模转换器（DAC）产生根据数字控制信号延迟的定时信号（例如，降频信号或参考时钟信号）的延迟版本。 相位检测器（PD）从降频信号和/或延迟的定时信号产生相位控制信号。 数字信号转换器控制数字可调分频器和相位DAC，以使由VCO输出的合成频率信号的相位或频率跟踪以数字信号编码的所需相位或频率轨迹。

公开(公告)号：US08222965B1

公开(公告)日：2012-07-17

申请号：US12877732

申请日：2010-09-08

申请人： Thor Nelson Juneau ,  Mark Alan Lemkin

发明人： Thor Nelson Juneau ,  Mark Alan Lemkin

IPC分类号： H03C3/06 ,  H03L7/08

CPC分类号： H03C3/0916 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0975 ,  H03C2200/0008

摘要： A modulator for modulating a radio frequency signal comprises a voltage controlled oscillator, a first feedback path, and a second feedback path. The first feedback path is coupled between a detector output and the voltage controlled oscillator. The second feedback path is coupled between the detector output and the voltage controlled oscillator. The detector is coupled to a divided down output of the voltage controlled oscillator and a reference clock.

摘要翻译： 用于调制射频信号的调制器包括压控振荡器，第一反馈路径和第二反馈路径。 第一反馈路径耦合在检测器输出和压控振荡器之间。 第二反馈路径耦合在检测器输出和压控振荡器之间。 检测器耦合到压控振荡器的分频输出和参考时钟。

公开(公告)号：US08170171B2

公开(公告)日：2012-05-01

申请号：US12356870

申请日：2009-01-21

申请人： Hiroyuki Kobayashi

发明人： Hiroyuki Kobayashi

IPC分类号： H03D3/24

CPC分类号： H03C3/0941 ,  H03C3/095 ,  H03C3/0975

摘要： A communication semiconductor integrated circuit, has: a first computing element which adds the count value and the phase difference value and outputs a first computed value as an addition result; a second computing element which adds set frequency data obtained by dividing a carrier frequency by a reference frequency of the reference signal and modulation frequency data obtained by dividing a modulation frequency by the reference frequency, and outputs a second computed value as an addition result; a third computing element which subtracts the second computed value from the first computed value and outputs a third computed value as a subtraction result, the third computed value being a phase error; and a fourth computing element which adds the carrier frequency control value and the modulation frequency control value, and outputs the oscillator tuning word as an addition result.

摘要翻译： 通信半导体集成电路具有：第一计算单元，其将计数值和相位差值相加，并输出第一计算值作为相加结果; 将通过将载波频率除以参考信号的参考频率而获得的设置频率数据和通过将调制频率除以参考频率获得的调制频率数据的第二计算元件，并输出第二计算值作为相加结果; 第三计算元件，其从所述第一计算值中减去所述第二计算值，并输出第三计算值作为减法结果，所述第三计算值是相位误差; 以及第四计算单元，其添加载波频率控制值和调制频率控制值，并输出振荡器调谐字作为相加结果。