公开(公告)号：US07319356B1

公开(公告)日：2008-01-15

申请号：US11303785

申请日：2005-12-16

Applicant: Mohammad Mahbubul Karim

Inventor： Mohammad Mahbubul Karim

IPC: H03K7/00

CPC classification number: H03M9/00 ,  H03K17/693 ,  H03K19/00315 ,  H03K19/018528 ,  H03K2005/00065

Abstract: A digitally controlled circuit is arranged to provide the combined functions of level shifting, multiplexing, and delay control functions. The circuit is compact, and uses lower power and lower overall noise susceptibility over other solutions. A programmable bias current is arranged to adjust the delay through the circuit. The bias current can be provided by a digitally controlled current source, a binary weighted current DAC, or other digitally controlled means. The multiplexing functions are provided by an input stage circuit that is current limited by the programmable bias current. An output stage is arranged to convert signals from the input stage to a desired voltage level.

Abstract translation: 数字控制电路被设置为提供电平转换，复用和延迟控制功能的组合功能。 该电路紧凑，与其他解决方案相比，功耗更低，总体噪音更低。 布置可编程偏置电流以调整通过电路的延迟。 偏置电流可以由数字控制的电流源，二进制加权电流DAC或其他数字控制装置提供。 多路复用功能由受可编程偏置电流限制的输入级电路提供。 输出级被布置成将来自输入级的信号转换成期望的电压电平。

公开(公告)号：US07317342B2

公开(公告)日：2008-01-08

申请号：US11224820

申请日：2005-09-13

Applicant: Martin Saint-Laurent

Inventor： Martin Saint-Laurent

IPC: G06F1/04

CPC classification number: G06F1/10 ,  H03K5/133 ,  H03K5/1506 ,  H03K2005/00039 ,  H03K2005/00065 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/085 ,  H03L7/0995

Abstract: A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the IC at respective local clock regions. A master clock generator generates a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions.

Abstract translation: 用于使用数字反馈进行偏移补偿和抖动滤波的集成电路（IC）中时钟分配的时钟分配网络。 在一个实施例中，多个时钟处理器节点分布在IC的各个本地时钟区域的整个时钟分配网络中。 主时钟发生器通过时钟分配网络产生主时钟，用于分配给时钟处理器节点，以补偿时钟偏移并且在相应的本地时钟区域局部滤波时钟抖动。

公开(公告)号：US20070285145A1

公开(公告)日：2007-12-13

申请号：US11843371

申请日：2007-08-22

Applicant: Jongtae Kwak

Inventor： Jongtae Kwak

IPC: H03H11/26

CPC classification number: H03L7/0814 ,  H03K5/133 ,  H03K19/01707 ,  H03K19/01721 ,  H03K2005/00052 ,  H03K2005/00065 ,  H03K2005/00215

Abstract: Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals.

Abstract translation: 描述包括时钟混合电路以提供可选择的传播时间的延迟电路。 来自混合电路的输出信号通过可变延迟线选择性耦合，以同步两个时钟信号。

公开(公告)号：US07307446B1

公开(公告)日：2007-12-11

申请号：US11510514

申请日：2006-08-24

Applicant: Sergey Y. Shumarayev ,  Thomas H. White ,  Rakesh H. Patel ,  Wilson Wong

Inventor： Sergey Y. Shumarayev ,  Thomas H. White ,  Rakesh H. Patel ,  Wilson Wong

IPC: H03K17/16

CPC classification number: H03K19/018585 ,  H03K5/06 ,  H03K5/13 ,  H03K5/151 ,  H03K2005/00032 ,  H03K2005/00065

Abstract: Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

Abstract translation: 提供了具有差分I / O电路的可编程逻辑器件集成电路。 差分I / O电路可以包括用于在输出线对之间提供差分数字输出数据信号的输出驱动器。 用户可以对I / O电路进行编程，以适应不同的高速差分I / O信号标准。 用户还可以对I / O电路进行编程，以向输出数据信号提供期望量的预加重。

公开(公告)号：US20070217481A1

公开(公告)日：2007-09-20

申请号：US11641140

申请日：2006-12-19

Applicant: JaeHong Ko ,  SeungJung Lee ,  Taekyoung Kim

Inventor： JaeHong Ko ,  SeungJung Lee ,  Taekyoung Kim

IPC: H04B1/00

CPC classification number: H03K5/133 ,  G06F1/08 ,  H03K3/84 ,  H03K2005/00065 ,  H03K2005/00071

Abstract: A method of generating a spread-spectrum clock signal includes delaying a high frequency clock signal to provide a plurality of delayed high frequency clock signals selected among to provide a spread-spectrum clock signal for a synchronous system.

Abstract translation: 产生扩频时钟信号的方法包括延迟高频时钟信号以提供多个延迟的高频时钟信号，以在同步系统中提供扩频时钟信号。

公开(公告)号：US07239494B2

公开(公告)日：2007-07-03

申请号：US10653760

申请日：2003-09-03

Applicant: Samuel D. Naffziger

Inventor： Samuel D. Naffziger

IPC: H02H9/00

CPC classification number: H03K5/08 ,  H03K17/0822 ,  H03K2005/00065

Abstract: A system and method can mitigate voltage fluctuations. According to one embodiment, a delay system provides a delayed version of a first reference signal as a function of a supply voltage. A comparator provides a control signal for controlling a protection device based on the delayed version of the first reference signal and a second reference signal. The amount of delay provided by the delay system defines a threshold based on which the comparator provides the control signal.

Abstract translation: 系统和方法可以减轻电压波动。 根据一个实施例，延迟系统提供作为电源电压的函数的第一参考信号的延迟版本。 比较器提供用于基于第一参考信号的延迟版本和第二参考信号来控制保护装置的控制信号。 由延迟系统提供的延迟量定义了基于比较器提供控制信号的阈值。

公开(公告)号：US20060279335A1

公开(公告)日：2006-12-14

申请号：US11125537

申请日：2005-05-09

Applicant: Noam Familia

Inventor： Noam Familia

IPC: H03K19/094

CPC classification number: H03K5/133 ,  H03K2005/00065

Abstract: A driver circuit in a phase interpolator is provided. In some embodiments, it comprises an input to receive an input clock signal, an output; and at least one pull-up and pull-down device coupled between the input and output to provide at the output the input clock signal driven at a desired level. The at least one pull-up and pull-down devices comprise a plurality of selectably engageable devices to drive the input clock signal at the desired level. Other embodiments are described and/or claimed herein.

Abstract translation: 提供了相位插值器中的驱动电路。 在一些实施例中，其包括用于接收输入时钟信号的输入端，输出端; 以及耦合在输入和输出之间的至少一个上拉和下拉装置，以在输出处提供以期望水平驱动的输入时钟信号。 所述至少一个上拉和下拉装置包括多个可选择地可接合的装置，以将所述输入时钟信号驱动到期望的水平。 在此描述和/或要求保护的其它实施例。

公开(公告)号：US07079615B2

公开(公告)日：2006-07-18

申请号：US09988691

申请日：2001-11-20

Applicant: Daniel William Bailey

Inventor： Daniel William Bailey

IPC: H03D3/24

CPC classification number: H03L7/0814 ,  H03K5/131 ,  H03K5/133 ,  H03K2005/00065 ,  H03L7/089 ,  H03L7/093

Abstract: A digital delay locked loop (DLL) includes a phase detector that measures the phase difference between a signal to be synchronized and a reference signal. The phase detector produces an increase or decrease signal in response to the phase difference between the two signals. This signal is received by a binary counter, which changes its count in response. The output of the binary counter is supplied to a comparator logic that implements a thermometer coding scheme. Each of the comparator output signals enables or disables a corresponding transistor stack in a delay line, thereby changing the delay of the signal propagating through the delay line.

公开(公告)号：US07034592B2

公开(公告)日：2006-04-25

申请号：US10851905

申请日：2004-05-21

Applicant: Takanori Saeki

Inventor： Takanori Saeki

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00071

Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

公开(公告)号：US06965262B2

公开(公告)日：2005-11-15

申请号：US10123370

申请日：2002-04-15

Applicant: Jared L. Zerbe

Inventor： Jared L. Zerbe

IPC: G11C7/10 ,  H04L7/033 ,  H04L25/02 ,  H04L25/03 ,  G06F7/64

CPC classification number: H04L25/0276 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C8/10 ,  H03K3/356034 ,  H03K5/131 ,  H03K5/133 ,  H03K17/162 ,  H03K19/00323 ,  H03K19/018528 ,  H03K2005/00065 ,  H03M5/20 ,  H04L7/0332 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/03878

Abstract: An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

Abstract translation: 一种用于接收具有低输入到输出等待时间的宽共模范围的高速信号的装置和方法。 在一个实施例中，接收机包括积分器，以在积分时间间隔期间根据输入信号累积电荷以产生输出电压。 读出放大器对积分器的输出电压进行采样并转换为逻辑信号; 并且锁存器存储逻辑信号。 在替代实施例中，前置放大器在被积分之前调节输入信号。 在使用多个接收机的另一实施例中，将电路添加到接收机以补偿与定时信号的分布相关联的定时误差。 在另一个实施例中，积分器耦合到补偿符号间干扰的均衡电路。 在另一个实施例中，另一个电路补偿积分器中的累积电压偏移误差。