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    CLOCK GATED FLIP-FLOP
    23.
    发明申请
    CLOCK GATED FLIP-FLOP 审中-公开

    公开(公告)号：US20170194945A1

    公开(公告)日：2017-07-06

    申请号：US15464600

    申请日：2017-03-21

    Applicant: MARVELL WORLD TRADE LTD.

    Inventor： Gideon PAUL

    IPC: H03K3/012 ,  H03K3/66 ,  H03K5/24 ,  H03K3/3562

    CPC classification number: H03K3/012 ,  H03K3/356121 ,  H03K3/35625 ,  H03K3/66 ,  H03K5/24

    Abstract: Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged.

    SIGNAL PROCESSING CIRCUIT
    24.
    发明申请
    SIGNAL PROCESSING CIRCUIT 有权

    公开(公告)号：US20170141770A1

    公开(公告)日：2017-05-18

    申请号：US15072613

    申请日：2016-03-17

    Applicant: SK hynix Inc.

    Inventor： Jae Hoon JUNG

    IPC: H03K3/66 ,  G11C7/22

    CPC classification number: H03K3/66 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225

    Abstract: A signal processing circuit may be provided. The signal processing circuit may include a mask generation circuit configured to output a mask signal in response to an internal control signal and masking information; and a masking circuit configured to mask the internal control signal in response to the mask signal, and output a masked control signal, wherein the mask generation circuit resets the mask signal in response to an internal reset signal, regardless of a pause polarity of the internal control signal.

    PULSE GENERATOR
    25.
    发明申请
    PULSE GENERATOR 审中-公开
    脉冲发生器

    公开(公告)号：US20140043083A1

    公开(公告)日：2014-02-13

    申请号：US14039610

    申请日：2013-09-27

    Applicant: Furukawa Automotive Systems Inc. ,  Furukawa Electric Co., Ltd.

    Inventor： Hiroki HIRAYAMA

    IPC: H03K3/013

    CPC classification number: H03K3/013 ,  G01S7/282 ,  H03F3/72 ,  H03K3/66 ,  H03K4/92 ,  H03K5/003 ,  H04B1/7174

    Abstract: Provided is a pulse generator that generates a pulse signal with a preferred waveform and offers increased isolation for a period of time when the pulse signal is not output.A pulse generator 100 allows a high-frequency oscillator 101 to output a high frequency signal and allows an amplifier 102 to amplify and output the signal. The amplifier 102 amplifies the high frequency signal from the high-frequency oscillator 101 and outputs the signal only for a period of time when its drive power is supplied by a drive circuit 110. The waveform of the drive power, supplied from the drive circuit 110 to the amplifier 102, is controlled by a waveform control unit 120 such that the high frequency signal amplified by the amplifier 102 becomes an ultra-wideband pulse signal.

    Abstract translation: 提供了一种脉冲发生器，其产生具有优选波形的脉冲信号，并且在不输出脉冲信号的一段时间内提供增加的隔离。 脉冲发生器100允许高频振荡器101输出高频信号，并允许放大器102放大并输出信号。 放大器102放大来自高频振荡器101的高频信号，并且仅在由驱动电路110提供驱动电力的时间段内输出该信号。从驱动电路110提供的驱动电力的波形 放大器102由波形控制单元120控制，使得由放大器102放大的高频信号成为超宽带脉冲信号。

    Template pulse generating circuit, communication device, and communication method
    26.
    发明授权
    Template pulse generating circuit, communication device, and communication method 有权
    模板脉冲发生电路，通讯装置及通讯方式

    公开(公告)号：US08031809B2

    公开(公告)日：2011-10-04

    申请号：US12038199

    申请日：2008-02-27

    Applicant: Izumi Iida

    Inventor： Izumi Iida

    IPC: H03K9/00

    CPC classification number: H03K3/66 ,  H04B1/71637 ,  H04B1/7174

    Abstract: A template pulse generating circuit that generates a template pulse used for detection of a received pulse in pulse communication includes an output mode switching circuit for switching an output mode in accordance with a supplied control signal between a continuous output mode that continuously outputs the template pulses and an intermittent output mode that intermittently outputs the template pulses so that the template pulse is generated in either one of the continuous output mode and the intermittent output mode.

    Abstract translation: 产生脉冲通信中用于检测接收脉冲的模板脉冲的模板脉冲发生电路包括：输出模式切换电路，用于根据连续输出模板脉冲的连续输出模式和连续输出模板脉冲的连续输出模式切换输出模式;以及 间歇输出模式，间歇地输出模板脉冲，使得在连续输出模式和间歇输出模式中的任一个中产生模板脉冲。

    Intermittent operation circuit and modulation device
    27.
    发明授权
    Intermittent operation circuit and modulation device 有权
    间歇运行电路和调制装置

    公开(公告)号：US07888984B2

    公开(公告)日：2011-02-15

    申请号：US12064446

    申请日：2006-08-23

    Applicant: Shigeru Kobayashi ,  Suguru Fujita

    Inventor： Shigeru Kobayashi ,  Suguru Fujita

    IPC: H03K3/00

    CPC classification number: H04B1/7174 ,  H03K3/66

    Abstract: There is provided a small-size, low-power-consumption intermittent operation circuit capable of obtaining an output waveform having a rapid rise and fall. The intermittent operation circuit includes an active circuit (106), a first control signal generation circuit (101) for generating a first control signal (S1) for controlling the operation start and the operation end of the active circuit (106), a second control signal generation circuit (102) for generating a second control signal (S2) causing the active circuit (106) to perform ringing vibration and controlling the frequency and the amplitude value of the ringing vibration, and a timing adjusting circuit (103) for adjusting the input timing of the first and the second control signal (S1, S2) into the active circuit (106) so that the ringing vibration and the safety vibration are outputted continuously from the active circuit (106).

    Abstract translation: 提供了能够获得快速上升和下降的输出波形的小尺寸，低功耗的间歇运行电路。 间歇运行电路包括有源电路（106），用于产生用于控制有源电路（106）的运行开始和运行结束的第一控制信号（S1）的第一控制信号发生电路（101） 信号发生电路（102），用于产生使有源电路（106）执行振铃振动并控制振铃的频率和振幅值的第二控制信号（S2），以及用于调整振铃振动的频率和振幅值的定时调整电路（103） 将所述第一和第二控制信号（S1，S2）的输入定时输入到所述有源电路（106）中，使得所述振铃和所述安全振动从所述有源电路（106）连续输出。

    Method and apparatus for increasing the speed of ultrasonic pulse-echo testing
    28.
    发明授权
    Method and apparatus for increasing the speed of ultrasonic pulse-echo testing 失效
    提高超声脉冲回波测试速度的方法和装置

    公开(公告)号：US4098131A

    公开(公告)日：1978-07-04

    申请号：US763865

    申请日：1977-01-31

    Applicant: Peter Renzel

    Inventor： Peter Renzel

    IPC: G01B17/02 ,  G01B21/08 ,  G01N29/07 ,  G01N29/44 ,  H03K3/66 ,  G01N29/04

    CPC classification number: G01B17/02 ,  G01N29/07 ,  G01N29/343 ,  H03K3/66 ,  G01N2291/02854

    Abstract: In order to increase the speed at which a workpiece is tested by the ultrasonic pulse-echo method, the dead time between individual measurement time intervals is shortened by providing a minimum predetermined time interval selected for the specific test conditions. When an echo responsive signal is manifest in the receiving circuit, in order to prevent the occurrence of phantom echo signals arising in the following measuring interval, the generation of the succeeding transmit signal is inhibited for the predetermined time interval after receipt of the last echo responsive electrical signal of the measuring interval having an amplitude exceeding a predetermined minimum amplitude. The test speed therefore, is made adaptive to the condition of the receipt of the number of echo responsive electrical signals exceeding a predetermined minimum amplitude.

    Abstract translation: 为了通过超声波脉冲 - 回波法提高工件的测试速度，通过提供针对具体测试条件选择的最小预定时间间隔来缩短各个测量时间间隔之间的死区时间。 当在接收电路中显示回波响应信号时，为了防止在随后的测量间隔中出现幻像回波信号的发生，在接收到最后一个回波响应之后，预定时间间隔的生成被抑制 测量间隔的电信号具有超过预定最小振幅的振幅。 因此，测试速度适应于接收超过预定最小振幅的回波响应电信号的数量的条件。

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