公开(公告)号：US10380945B2

公开(公告)日：2019-08-13

申请号：US15826377

申请日：2017-11-29

Applicant: SILICON WORKS CO., LTD.

Inventor： Dong Hyun Hwang ,  Se Won Lee

IPC: G09G3/32 ,  G09G3/3241 ,  G05F3/16 ,  G09G3/00 ,  G09G3/3233

Abstract: The present invention provides a technology of simultaneously sensing characteristics of a plurality of OLED pixels. Further, a current mirroring circuit for sensing characteristics of OLED pixels can be applied to fields other than sensing characteristics of OLED pixels, and the current mirroring technology can output sensing currents having a uniform magnitude within a predetermined error range to a plurality of output terminals.

公开(公告)号：US10249348B2

公开(公告)日：2019-04-02

申请号：US15663545

申请日：2017-07-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hitoshi Tanaka ,  Yasunori Orito

IPC: G11C5/14 ,  G05F3/26 ,  G05F3/16 ,  G05F1/46 ,  G05F1/10

Abstract: Apparatuses and methods for generating a voltage are described. An example apparatus includes first, second, and third bias circuits configured to provide first, second, and third bias signals, respectively. The example apparatus further includes a voltage output circuit configured to receive the first, second, and third bias signals. The voltage output circuit includes an output circuit and a current circuit. The output circuit includes an output node, a first node, and an input circuit configured to receive the first bias signal. The output circuit is configured to provide an output voltage at the output node having a magnitude based on the magnitude of the first bias signal. The current circuit includes a first transistor configured to receive the second bias signal and further includes a second transistor configured to receive the third bias signal. The first transistor and second transistor are coupled in parallel and to the first node.

公开(公告)号：US20190058487A1

公开(公告)日：2019-02-21

申请号：US16079546

申请日：2017-02-23

Applicant: ams AG

Inventor： Gonggui XU

IPC: H03M1/68 ,  G05F3/16

CPC classification number: H03M1/68 ,  G05F3/16 ,  H03M1/682 ,  H03M1/687 ,  H03M1/747

Abstract: A digital-to-analog converter comprises a converter output (11), a dummy output (12), a first number N of current sources (13-17), a first switching arrangement (18), a first current divider (24), a second switching arrangement (31) and a second current divider (60). The current sources (13-17) are coupled via the first switching arrangement (18) to the converter output (11), the dummy output (12) or to an input current terminal (25) of the first current divider (24). The output current terminals (26-30) of the first current divider (24) are coupled via the second switching arrangement (31) to the converter output (11), the dummy output (12) or to an input current terminal (61) of the second current divider (60). The output current terminals (63-66) of the second current divider (60) are coupled to the converter output (11) or the dummy output (12).

公开(公告)号：US10187011B2

公开(公告)日：2019-01-22

申请号：US15713145

申请日：2017-09-22

Applicant: STMicroelectronics International N.V.

Inventor： Vinod Kumar

IPC: H01L27/108 ,  H01L29/94 ,  H03F1/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  G05F3/16 ,  H03K17/687 ,  H03L7/093 ,  H03F3/193 ,  H01L29/786

Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

公开(公告)号：US20180356852A1

公开(公告)日：2018-12-13

申请号：US16106476

申请日：2018-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yvonne Lin ,  Da-Wen Lin ,  Peter Huang ,  Paul Rousseau ,  Sheng-Jier Yang

IPC: G05F3/16 ,  H01L29/78 ,  H01L29/06 ,  G05F1/595 ,  G05F1/46 ,  H01L21/8234 ,  H01L27/088

Abstract: Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.

公开(公告)号：US10148255B2

公开(公告)日：2018-12-04

申请号：US14883525

申请日：2015-10-14

Applicant: pSemi Corporation

Inventor： Mark L. Burgener ,  Dylan J. Kelly ,  James S. Cable

IPC: H02M3/18 ,  G05F3/16 ,  H03B5/00 ,  H03K3/013 ,  H02M3/07 ,  H03K3/03

Abstract: A charge pump method and apparatus is described having various aspects. Noise injection from a charge pump to other circuits may be reduced by limiting both positive and negative clock transition rates, as well as by limiting drive currents within clock generator driver circuits, and also by increasing a control node AC impedance of certain transfer capacitor coupling switches. A single-phase clock may be used to control as many as all active switches within a charge pump, and capacitive coupling may simplify biasing and timing for clock signals controlling transfer capacitor coupling switches. Any combination of such aspects of the method or apparatus may be employed to quiet and/or simplify charge pump designs over a wide range of charge pump architectures.

公开(公告)号：US10146240B1

公开(公告)日：2018-12-04

申请号：US15886700

申请日：2018-02-01

Applicant: Apple Inc.

Inventor： Ruopeng Wang ,  Dashun Xue ,  Jiandong Jiang ,  Jay B. Fletcher

IPC: G05F3/16 ,  G05F1/575 ,  H02M7/10 ,  G05F3/24

Abstract: A voltage regulator having a pre-regulator circuit is disclosed. A low dropout (LDO) voltage regulator includes an amplifier circuit, a current buffer circuit, and a pre-regulator circuit. The current buffer circuit includes a transistor having a gate terminal coupled to the amplifier output. The current buffer provides a current based at least in part on the output signal generated by the amplifier. The pre-regulator circuit is coupled to provide a dynamic supply voltage to the current buffer. They dynamic supply voltage depends at least in part on a fixed supply voltage provided thereto, as well as the output voltage provided by the LDO voltage regulator.

公开(公告)号：US10139849B2

公开(公告)日：2018-11-27

申请号：US15497051

申请日：2017-04-25

Applicant: Honeywell International Inc.

Inventor： Xiaoxin Feng ,  Weston Roper

IPC: H03F3/00 ,  G05F3/26 ,  G05F3/16 ,  G05F1/10 ,  G05F3/30 ,  G05F3/24 ,  H03K17/082 ,  H03K19/003 ,  H03K5/00

Abstract: The disclosure is directed to a simple, inexpensive circuit to extract the complementary metal-oxide-semiconductor (CMOS) threshold voltage (Vt) from an integrated circuit. The threshold voltage may be used elsewhere in the circuit for a variety of purposes. One example use of threshold voltage is to sense the temperature of the circuit. The CMOS Vt extraction circuit of this disclosure includes a current mirror and an arrangement of well-matched transistors and resistors that takes advantage of the square law equation. The structure of the circuit may make it well suited to applications that benefit from low-power radiation hardened circuits.

公开(公告)号：US10120405B2

公开(公告)日：2018-11-06

申请号：US14245693

申请日：2014-04-04

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Christopher G. Regier

IPC: H01L29/66 ,  G05F3/16

Abstract: A single semiconductor-based junction may be used to create a voltage reference, and temperature compensate the voltage reference, by time-multiplexing the voltage reference between different current drive levels. That is, the value of the current driven through the single junction may be repeatedly varied in a recurring manner. In case the junction is a zener diode, the current may be repeatedly switched between forward and reverse directions. As long as the temperature coefficients (in ppm/° C.) of the different voltages developed responsive to the different currents across the junction are different, a weighting of the different voltage values yield a zero temperature coefficient voltage reference value. To implement a bandgap reference, a single diode-connected bipolar junction transistor may alternately be forward-biased using a first current and at least a second current. A weighting of the (at least) two resulting Vbe (base-emitter voltage) drops may yield a zero temperature coefficient bandgap voltage.

公开(公告)号：US10095259B1

公开(公告)日：2018-10-09

申请号：US13789908

申请日：2013-03-08

Applicant: Skyworks Solutions, Inc.

Inventor： Rui Filipe Antunes Ribafeita ,  Michael Wayne Trippe

IPC: G05F3/04 ,  G05F3/16

Abstract: An electronic current mirror circuit particularly suitable for use in radio frequency (RF) and microwave power amplifiers. The electronic circuit includes a first current mirror circuit and a second current mirror circuit. The first current mirror circuit includes a first input circuit path and a first output circuit path, the first input circuit path is operated at a first supply voltage and the first output circuit path is operated at a second supply voltage. The second current mirror circuit includes a second input circuit path and a second output circuit path, the second input circuit path is operated at the second supply voltage, and the second output circuit path is connected to the first input circuit path so that variations in a current through the first output circuit path are compensated by a current in the second output circuit path.