公开(公告)号：US20040133741A1

公开(公告)日：2004-07-08

申请号：US10720162

申请日：2003-11-25

Applicant: NEC CORPORATION

Inventor： Atsushi Kuwata

IPC: G06F012/08

CPC classification number: G06F11/1076 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2211/1009 ,  G06F2211/1019 ,  G06F2211/1059 ,  G06F2212/1032 ,  G06F2212/262

Abstract: A disk array apparatus includes a cache memory for temporarily storing data to be read from or written to disks, and a control unit. The control unit associates data associated with logical addresses with physical addresses, writes the data associated with physical address in the cache memory and processes preferentially for writing the data associated with the physical addresses in the cache memory to the disks.

Abstract translation: 磁盘阵列装置包括用于临时存储要从盘读取或写入盘的数据的高速缓冲存储器，以及控制单元。 控制单元将与逻辑地址相关联的数据与物理地址相关联，将与物理地址相关联的数据写入高速缓冲存储器，并优先处理将与高速缓冲存储器中的物理地址相关联的数据写入磁盘。

公开(公告)号：US20040107328A1

公开(公告)日：2004-06-03

申请号：US10723781

申请日：2003-11-26

Inventor： Russell Alvin Schultz ,  Thomas A. Zudock

IPC: G06F012/08

CPC classification number: G06F9/445 ,  G06F9/44557 ,  G06F12/0223

Abstract: An internal memory uses a resource identifier and an entry point to identify which functional program from an external memory is to be loaded into one of a plurality of overlay spaces established in the internal memory. In executing a program statement, the resource identifier identifies a corresponding functional program to perform a particular functional operation and the identified functional program is then loaded into an overlay space specified by the entry point. The functional program is then executed in the overlay space.

Abstract translation: 内部存储器使用资源标识符和入口点来识别来自外部存储器的哪个功能程序将被加载到在内部存储器中建立的多个重叠空间之一中。 在执行程序语句时，资源标识符识别相应的功能程序以执行特定的功能操作，然后将所识别的功能程序加载到由入口点指定的覆盖空间中。 然后在叠加空间中执行功能程序。

公开(公告)号：US20040107321A1

公开(公告)日：2004-06-03

申请号：US10676540

申请日：2003-10-01

Inventor： Erik R. Altman ,  Peter G. Capek ,  Michael Karl Gschwind ,  Harm Peter Hofstee ,  James Allan Kahle ,  Ravi Nair ,  Sumedh Wasudeo Sathaye ,  John-David Wellman

IPC: G06F012/08

CPC classification number: G06F12/1027 ,  G06F2212/682

Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract translation: 用于在SMP系统中访问共享存储器的附加处理单元的方法和系统。 在一个实施例中，系统包括共享存储器。 该系统还包括耦合到共享存储器的多个处理元件。 多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。 每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。 每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。 相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

公开(公告)号：US20040093469A1

公开(公告)日：2004-05-13

申请号：US10291895

申请日：2002-11-08

Applicant: Newisys, Inc. A Delaware corporation

Inventor： David B. Glasco

IPC: G06F012/08

CPC classification number: G06F12/0815

Abstract: Methods and devices are provided for controlling lock and unlock operations within a computer system. A home cluster includes a home lock manager. The home lock manager is a master lock manager for the home cluster and for a plurality of remote clusters, the plurality of remote clusters including remote cache coherency controllers and a plurality of remote processors. Lock and unlock commands from the home lock manager are transmitted by a home cache coherency controller to the remote cache coherency controllers and forwarded to the remote processors.

Abstract translation: 提供了用于控制计算机系统内的锁定和解锁操作的方法和装置。 家庭集群包括家庭锁管理员。 归属锁管理器是主集群和多个远程集群的主锁管理器，多个远程集群包括远程高速缓存一致性控制器和多个远程处理器。 来自家庭锁管理器的锁定和解锁命令由家庭高速缓存一致性控制器传输到远程高速缓存一致性控制器并转发给远程处理器。

公开(公告)号：US20040093467A1

公开(公告)日：2004-05-13

申请号：US10325028

申请日：2002-12-19

Applicant: Massachusetts Institute of Technology, a Massachusetts corporation

Inventor： Xiaowei Shen ,  Arvind Mithal ,  Lawrence Rogel

IPC: G06F012/08

CPC classification number: G06F12/0826 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0817

Abstract: A methodology for designing a distributed shared-memory system, which can incorporate adaptation or selection of cache protocols during operation, guarantees semantically correct processing of memory instructions by the multiple processors. A set of rules includes a first subset of nullmandatorynull rules and a second subset of nullvoluntarynull rules such that correct operation of the memory system is provided by application of all of the mandatory rules and selective application of the voluntary rules. A policy for enabling voluntary rules specifies a particular coherent cache protocol. The policy can include various types of adaptation and selection of different operating modes for different addresses and at different caches. A particular coherent cache protocol can make use of a limited capacity directory in which some but not necessarily all caches that hold a particular address are identified in the directory. In another coherent cache protocol, various caches hold an address in different modes which, for example, affect communication between a cache and a shared memory in processing particular memory instructions.

Abstract translation: 用于设计分布式共享存储器系统的方法，其可以在操作期间结合适应或选择高速缓存协议，保证了多处理器对存储器指令的语义上正确的处理。 一组规则包括“强制性”规则的第一子集和“自愿”规则的第二子集，从而通过应用所有强制性规则并选择性地应用自愿规则来提供存储系统的正确操作。 启用自愿规则的策略规定了特定的一致高速缓存协议。 该策略可以包括各种类型的适配和针对不同地址和不同高速缓存的不同操作模式的选择。 特定的一致高速缓存协议可以使用有限容量的目录，其中在目录中识别出一些但不一定所有保存特定地址的高速缓存。 在另一个相干高速缓存协议中，各种高速缓存以不同的模式保存地址，这些地址例如在处理特定的存储器指令时影响高速缓存和共享存储器之间的通信。

公开(公告)号：US20040088491A1

公开(公告)日：2004-05-06

申请号：US10693303

申请日：2003-10-24

Inventor： Norman Paul Jouppi ,  Keith Istvan Farkas

IPC: G06F012/08

CPC classification number: G06F9/3802 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30189 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3863 ,  G06F12/0862 ,  G06F2212/6022

Abstract: A microprocessor is configured to continue execution in a special Speculative Prefetching After Data Cache Miss (SPAM) mode after a data cache miss is encountered. The microprocessor includes additional registers and program counter, and optionally additional cache memory for use during the special SPAM mode. By continuing execution during the SPAM mode, multiple outstanding and overlapping cache fill requests may be issued, thus improving performance of the microprocessor.

Abstract translation: 微处理器被配置为在遇到数据高速缓存未命中之后，以特殊的数据高速缓存丢失（SPAM）预取预取模式继续执行。 微处理器包括附加的寄存器和程序计数器，以及可选地在特殊的SPAM模式期间使用的另外的高速缓存。 通过在SPAM模式期间继续执行，可以发出多个未完成和重叠的高速缓存填充请求，从而提高微处理器的性能。

公开(公告)号：US20040062068A1

公开(公告)日：2004-04-01

申请号：US10664455

申请日：2003-09-18

Inventor： Keenan W. Franz ,  Michael T. Vaden

IPC: G11C005/00 ,  G06F012/08

CPC classification number: G06F12/0802 ,  G06F2212/601 ,  G11C2207/104 ,  G11C2207/2245

Abstract: A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.

公开(公告)号：US20040059873A1

公开(公告)日：2004-03-25

申请号：US10628434

申请日：2003-07-29

Inventor： Herbert Hing-Jing Hum ,  Zohar Bogin

IPC: G06F012/08

CPC classification number: G06F12/0862 ,  G06F2212/6026

Abstract: An apparatus and method for prefetching cache data in response to data requests. The prefetching uses the memory addresses of requested data to search for other data, from a related address, in a cache. This, or other data, may then be prefetched based on the result of the search.

Abstract translation: 一种用于响应于数据请求预取缓存数据的装置和方法。 预取使用请求的数据的存储器地址从缓存中的相关地址搜索其他数据。 然后可以基于搜索的结果来预取这个或其他数据。

公开(公告)号：US20040044847A1

公开(公告)日：2004-03-04

申请号：US10232248

申请日：2002-08-29

Applicant: International Business Machines Corporation

Inventor： David Scott Ray ,  David J. Shippy

IPC: G06F012/00 ,  G06F012/08

CPC classification number: G06F12/0859 ,  G06F9/30047 ,  G06F12/0862 ,  G06F12/0897

Abstract: This invention provides a dual usage cache reload buffer (CRB) to hold both demand loads as well as prefetch loads. A new form of a data cache block touch (DCBT) instruction specifies which level of the cache hierarchy to prefetch data into. A first asynchronous form of a DCBT instruction is issued to prefetch a stream of data into a L2 cache. A second synchronous form of a DCBT instruction is used to prefetch data from the L2 cache to the CRB in the main CPU, which will bypass the L1 data cache and forward data directly to the register file. This CRB has a dual usage and is used to hold both normal cache reloads as well as the aforementioned prefetched cache lines.

Abstract translation: 本发明提供了一种双重使用高速缓存重载缓冲器（CRB），用于保存需求负载以及预取负载。 数据高速缓存块触摸（DCBT）指令的新形式指定要将数据预取到哪个级别的缓存层次结构。 颁发DCBT指令的第一种异步形式，以将数据流预取到L2高速缓存中。 DCBT指令的第二种同步形式用于将数据从L2高速缓存预取到主CPU中的CRB，这将绕过L1数据高速缓存并将数据直接转发到寄存器文件。 该CRB具有双重用途，用于保存正常缓存重新加载以及上述预取缓存行。

公开(公告)号：US20040030836A1

公开(公告)日：2004-02-12

申请号：US10635684

申请日：2003-08-07

Applicant: ARM Limited

Inventor： Ian Victor Devereux

IPC: G06F012/08

CPC classification number: G06F12/126

Abstract: The present invention relates to the management of caches in a data processing apparatus, and in particular to the management of caches of the type where data in the cache may be designated as locked to prevent that data from being overwritten. The data processing apparatus comprises a processor, an n-way set associative cache having a plurality of entries, each entry being arranged to store one or more data values and a corresponding address identifier, the processor being operable to select one or more of the n-ways to operate in a lockdown mode, the lockdown mode being used to lock data values into the corresponding way, and a plurality of lockdown controllers. Each lockdown controller is associated with a corresponding way and comprises an address register arranged to store an address range specified by the processor such that, when the corresponding way is in the lockdown mode, only data values whose address identifiers are within the address range are locked into the corresponding way. This technique provides for reduced complexity during lockdown because in preferred embodiments a dedicated lockdown program is not required to carefully manage the storage of data values in the lockdown, the lockdown occurs automatically.

Abstract translation: 本发明涉及一种数据处理装置中的高速缓存的管理，特别涉及对高速缓存中的数据被指定为锁定的类型的高速缓存的管理，以防止该数据被覆盖。 数据处理装置包括处理器，具有多个条目的n路组相关高速缓存，每个条目被布置为存储一个或多个数据值和对应的地址标识符，所述处理器可操作以选择n个中的一个或多个 在锁定模式下操作，锁定模式用于将数据值锁定到相应的方式，以及多个锁定控制器。 每个锁定控制器与相应的方式相关联并且包括地址寄存器，其被布置为存储由处理器指定的地址范围，使得当对应的方式处于锁定模式时，仅地址标识符在地址范围内的数据值被锁定 进入相应的方式。 这种技术在锁定期间提供降低的复杂性，因为在优选实施例中，不需要专门的锁定程序来仔细管理锁定中的数据值的存储，所以自动发生锁定。