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公开(公告)号：US20240333268A1
公开(公告)日：2024-10-03
申请号：US18739876
申请日：2024-06-11
发明人： Huaixin XIAN , Longbiao LEI , Senpei GOA , Zhang-Ying YAN , Qingchao MENG , Jerry Chang Jui KAO
CPC分类号： H03K3/86 , H03K3/0375 , H03K3/356113
摘要： A method of forming a semiconductor device includes forming a first row of transistors extending in a first direction and including dummy transistors and active transistors. The first row includes, in a sequence from a first end to a second end, at least a first dummy group, a first delay cell, a second delay cell, and a second dummy group. The first dummy group is formed of one or more dummy transistors. The second dummy group is formed of one or more dummy transistors. The first delay cell is formed of active transistors configured as a basic inverter and a float-resistant inverter. The second delay cell is formed of active transistors configured as at least one inverter. The first row is free of dummy transistors between the first delay cell and the second delay cell.
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公开(公告)号：US20240056062A1
公开(公告)日：2024-02-15
申请号：US17822559
申请日：2022-08-26
发明人： Huaixin XIAN , Longbiao LEI , Sinpei GOA , Zhang-Ying YAN , Qingchao MENG , Jerry Chang Jui KAO
CPC分类号： H03K3/86 , H03K3/0375 , H03K3/356113
摘要： A semiconductor device includes a first dummy group having a first set of dummy transistors; a first delay cell having a first set of active transistors; a second delay cell having a second set of active transistors; a second dummy group having a second set of dummy transistors; and relative to a first direction the first and second dummy groups and the first and second delay cells being arranged in a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group; and the first and second delay cells being free from having another dummy group therebetween.
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公开(公告)号：US20230079802A1
公开(公告)日：2023-03-16
申请号：US17693864
申请日：2022-03-14
申请人： Kioxia Corporation
发明人： Masashi NAKATA
IPC分类号： H03K3/017 , H03K3/86 , H03K3/0233 , G11C7/22 , G11C8/18
摘要： A semiconductor integrated circuit of an embodiment includes: a delay element array circuit in which a plurality of delay elements having a delay amount Tw are connected in series; a flip-flop group including a plurality of flip-flops each of which an input is connected to an output of a corresponding delay element; a delay element group configured to generate, from an input clock signal, a plurality of output clock signals each having a delay difference of a second delay amount smaller than the delay amount Tw; and a delay unit configured to set a third delay amount smaller than the second delay amount, and the delay element group and the delay unit are connected in series between an output terminal of an input signal CLK_DET and an input terminal of the flip-flop group.
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公开(公告)号：US20210167761A1
公开(公告)日：2021-06-03
申请号：US17045276
申请日：2019-05-07
发明人： Jieyao LIU , Nangeng ZHANG , Jingjie WU , Shenghou MA
摘要： The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.
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公开(公告)号：US08963603B2
公开(公告)日：2015-02-24
申请号：US14245515
申请日：2014-04-04
发明人： Shih-Hsiun Huang , Shian-Ru Lin
CPC分类号： H03K3/86 , H03K5/15013
摘要： A clock generation device includes a first delay unit, a frequency divider, an angle delay unit and a first calculating unit. The first delay unit receives an input clock and delays the input clock by a first preset period to generate an input delay clock. The frequency divider divides a frequency of the delay clock to generate a first frequency-divided clock and a second frequency-divided clock. A frequency of each of the first frequency-divided clock and the second frequency-divided clock is a preset multiple of the input delay clock. The angle delay unit delays the first frequency-divided clock by a second preset period to generate a first delay clock. The first calculating unit determines a trigger time of a first edge of a first output clock with reference to voltage levels of the first frequency-divided clock and the first delay clock and determines a falling time of a second edge of the first output clock with reference to voltage levels of the input clock and the first delay clock.
摘要翻译： 时钟发生装置包括第一延迟单元，分频器，角度延迟单元和第一计算单元。 第一延迟单元接收输入时钟并将输入时钟延迟第一预设周期以产生输入延迟时钟。 分频器分频延迟时钟的频率以产生第一分频时钟和第二分频时钟。 第一分频时钟和第二分频时钟中的每一个的频率是输入延迟时钟的预设倍数。 角度延迟单元将第一分频时钟延迟第二预设周期以产生第一延迟时钟。 第一计算单元参考第一分频时钟和第一延迟时钟的电压电平来确定第一输出时钟的第一边沿的触发时间，并且以参考的方式确定第一输出时钟的第二边缘的下降时间 到输入时钟和第一延迟时钟的电压电平。
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公开(公告)号：US08933742B2
公开(公告)日：2015-01-13
申请号：US13890649
申请日：2013-05-09
CPC分类号： H03K3/86 , H03K5/13 , H03K2005/00032 , H03K2005/00052
摘要： Time-Mode Signal Processing (TMSP) offers a means for offsetting some of the challenges for analog circuit designs when exploiting CMOS circuit processes designed for digital applications. It would therefore be beneficial to provide a digital method for the storage, addition and subtraction of Time-Mode variables as these offer significant benefit to providing TMSP techniques and expanding their exploitation within devices, systems, and applications. While driven by CMOS process challenges the TM circuits outlined may exploit essentially any digital circuit technology since they are based upon delay. The inventors present an approach to TM variables wherein a switched delay unit is exploited and adopted such that the instantaneous phase difference between two rising signal edges can be latched and used to perform various arithmetic operations. Beneficially, the technique allows analog sampled-data signal processing to be implemented within digital circuitry.
摘要翻译： 时间模式信号处理（TMSP）提供了一种在利用为数字应用设计的CMOS电路工艺时，抵消模拟电路设计中的一些挑战的手段。 因此，提供用于存储，加减时间模式变量的数字方法将是有益的，因为它们提供了提供TMSP技术并扩展其在设备，系统和应用中的利用的显着优点。 在CMOS工艺挑战的驱动下，TM电路基本上可以利用任何数字电路技术，因为它们基于延迟。 本发明人提出了一种TM变量的方法，其中开关和采用开关延迟单元，使得两个上升信号边沿之间的瞬时相位差可被锁存并用于执行各种算术运算。 有利的是，该技术允许在数字电路内实现模拟采样数据信号处理。
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公开(公告)号：US20120274375A1
公开(公告)日：2012-11-01
申请号：US13543724
申请日：2012-07-06
申请人： Teik Wah Lim , Eng Huat Lee , Ie Chen Chia , Thow Pang Chong , Boon Jin Ang , Kim Pin Tan
发明人： Teik Wah Lim , Eng Huat Lee , Ie Chen Chia , Thow Pang Chong , Boon Jin Ang , Kim Pin Tan
CPC分类号： H03L7/081 , G11C17/16 , G11C29/023 , G11C29/028 , G11C2029/4402 , H03L7/08
摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.
摘要翻译： 公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。 所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。 控制块读取存储在可编程保险丝中的设置或数据。 耦合到控制块的调谐电路接收由控制块发送的延迟。 调谐电路允许调节IC而不改变制造掩模。 调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。
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公开(公告)号：US20050101265A1
公开(公告)日：2005-05-12
申请号：US10702036
申请日：2003-11-06
申请人： Mladen Kekez , Daniel Kekez
发明人： Mladen Kekez , Daniel Kekez
CPC分类号： H03K3/86
摘要： A device for generating and radiating radio frequencies. The device includes a transmission line, a source, and a means for applying a voltage impulse to the transmission line from a low impedance source. A quarter-wave trap is added between the source and the transmission line to suppress the onset of a parasitic radiating mode. The quarter-wave trap also acts as an antenna to transmit the energy to the surrounding environment from the transmission line, which is behaving as an oscillatory circuit. The low impedance source is an electrically driven impulse generator. As a further modification, a second antenna can be attached to the free end of the transmission line to enable lower frequencies to be transmitted.
摘要翻译： 用于产生和辐射射频的装置。 该装置包括传输线，源极和用于从低阻抗源向传输线施加电压脉冲的装置。 在源极和传输线之间增加一个四分之一波形阱，以抑制寄生辐射模式的开始。 四分之一波形陷波器还用作将天线从传输线传输到周围环境的天线，传输线作为振荡电路。 低阻抗源是电驱动脉冲发生器。 作为进一步的修改，第二天线可以附接到传输线的自由端，以便能够传输更低的频率。
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公开(公告)号：US6049241A
公开(公告)日：2000-04-11
申请号：US30296
申请日：1998-02-25
申请人： Brian L. Brown , Roger D. Norwood
发明人： Brian L. Brown , Roger D. Norwood
CPC分类号： G06F1/10
摘要： A clock circuit including an input terminal (300) for receiving a clock signal and a first pulse generator (302) coupled to the input terminal. The first pulse generator is operable to generate a voltage pulse in response to a logic-low voltage to logic-high voltage transition of the clock signal. The circuit also includes a second pulse generator (304) coupled to the input terminal, the second pulse generator being operable to generate a voltage pulse in response to a logic-high voltage to logic-low voltage transition of the clock signal. A first clock deskewing circuit (306) is coupled between the first pulse generator and a first clock signal output terminal and a second clock deskewing circuit (308) is coupled between the second pulse generator and a second clock signal output terminal. The circuit may also include an OR logic circuit (310) coupled to the first and second clock signal output terminals, and a third pulse generator (312) coupled to the OR logic circuit, the third pulse generator having a third clock signal output terminal (314).
摘要翻译： 一种时钟电路，包括用于接收时钟信号的输入端（300）和耦合到输入端的第一脉冲发生器（302）。 第一脉冲发生器可操作以响应于时钟信号的逻辑 - 高电压转换的逻辑低电压而产生电压脉冲。 电路还包括耦合到输入端子的第二脉冲发生器（304），第二脉冲发生器可操作以响应于时钟信号的逻辑 - 低电压转换的逻辑高电压而产生电压脉冲。 第一时钟歪斜电路（306）耦合在第一脉冲发生器和第一时钟信号输出端之间，第二时钟偏移校正电路（308）耦合在第二脉冲发生器和第二时钟信号输出端之间。 电路还可以包括耦合到第一和第二时钟信号输出端的OR逻辑电路（310）和耦合到或逻辑电路的第三脉冲发生器（312），第三脉冲发生器具有第三时钟信号输出端（ 314）。
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30.发明授权Electromagnetic generator for fast current and magnetic field pulses, for example, for use in magnetic metal working 失效用于快速电流和磁场脉冲的电磁发生器，例如用于磁性金属加工
公开(公告)号：US5684341A
公开(公告)日：1997-11-04
申请号：US282738
申请日：1994-07-29
申请人： Erich Steingroever
发明人： Erich Steingroever
摘要： An electromagnetic generator for working electrically conducting objects with current and magnetic field pulses having a high rate of rise as expressed by dI/dt and dB/dt includes primary windings of a pulse transformer that are arranged in pairs so that their primary currents generate a single current pulse on the secondary side of the pulse transformer. The pulse transformer has as secondary coil comprised of a longitudinally slit pipe on which the insulated primary windings are placed. Contact blocks are attached as current outputs next to the longitudinal slit and in the middle of pipe for the connection of an external low-ohmic peak-current loop which encloses a magnetic field concentrator that is made in one or several parts and that can accept one or several metal work pieces.
摘要翻译： 用于工作电导物体的电磁发生器具有由dI / dt和dB / dt表示的具有高升高速率的电流和磁场脉冲，包括成对布置的脉冲变压器的初级绕组，使得其初级电流产生单个 脉冲变压器次级侧的电流脉冲。 脉冲变压器具有由纵向狭缝管组成的次级线圈，绝缘初级绕组放置在该狭缝管上。 接触块作为电流输出连接在纵向狭缝旁边和管道中间，用于连接外部低欧姆峰值电流回路，外部低电阻峰值电流回路包含一个或多个部件制成的磁场集中器，并可接受一个 或几个金属工件。
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