公开(公告)号：US20230079155A1

公开(公告)日：2023-03-16

申请号：US17990749

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L29/786 ,  H01L27/092

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first transistor is formed on a substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions.

公开(公告)号：US20230073022A1

公开(公告)日：2023-03-09

申请号：US17987867

申请日：2022-11-16

Applicant: United Microelectronics Corp.

Inventor： Nuo Wei Luo ,  Huabiao Wu

IPC: H01L21/68 ,  H01L21/027 ,  G03F7/20 ,  H01L23/544

Abstract: Provided is a semiconductor device includes a substrate, an isolation structure, an alignment mark, and a dielectric layer. The substrate includes a first region and a second region. The isolation structure is disposed in the substrate in the first region, wherein the isolation structure extends from a first surface of the substrate toward a second surface of the substrate.
The alignment mark is disposed in the substrate in the second region. The alignment mark extends from the first surface of the substrate toward the second surface of the substrate and at the same level as the isolation structure. The dielectric layer is buried in the substrate in the second region and overlapping the alignment mark.

公开(公告)号：US20230058811A1

公开(公告)日：2023-02-23

申请号：US17981499

申请日：2022-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Chi-Mao Hsu ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Chun-Hsien Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

公开(公告)号：US20230058468A1

公开(公告)日：2023-02-23

申请号：US17409756

申请日：2021-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： BO TAO ,  RUNSHUN WANG ,  Li Wang ,  Ching-Yang Wen ,  Purakh Raj Verma ,  DONG YIN ,  Jian Xie

IPC: H01L21/768

Abstract: A method of fabricating an air gap includes receiving a first thickness information of an inter-metal dielectric layer formed on a substrate and receiving a second thickness information of an inter-layer dielectric layer formed on the substrate. Then, a first etching is performed, wherein the first etching includes etch the inter-metal dielectric layer based on a first etching control value corresponding to the first thickness information. After the first etching, a second etching is performed to etch the inter-layer dielectric layer based on a second etching control value corresponding to the second thickness information.

公开(公告)号：US11581422B2

公开(公告)日：2023-02-14

申请号：US17161707

申请日：2021-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/66 ,  H01L21/762

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

公开(公告)号：US20230043723A1

公开(公告)日：2023-02-09

申请号：US17970590

申请日：2022-10-21

Applicant: United Microelectronics Corp.

Inventor： Chih-Yuan Chung ,  Te-Chang Wu

IPC: H02H3/08 ,  H02H3/06

Abstract: An electrostatic discharge (ESD) circuit is used to protect an internal circuit. The ESD circuit includes: an ESD clamp, having a first terminal connected to a power and a second terminal connected to a ground voltage; and a first switch, connected between an ESD terminal of the ESD clamp and the internal circuit. A gate of the first switch is controlled by a state signal in the ESD clamp to turn off the first switch when an ESD event occurs on the first terminal of the ESD clamp and turn on the first switch when the ESD event does not occur.

公开(公告)号：US20230038528A1

公开(公告)日：2023-02-09

申请号：US17967904

申请日：2022-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H01L43/02 ,  G11C5/06 ,  H01L43/12 ,  G11C11/16 ,  H01L29/82 ,  H01L43/08 ,  H01L27/22

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

公开(公告)号：US11569355B1

公开(公告)日：2023-01-31

申请号：US17470801

申请日：2021-09-09

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

Abstract: A method of manufacturing a memory structure including following steps is provided. Two gate stack structures are formed on a substrate. A conductive material layer is conformally formed on the two gate stack structures. The conductive material layer includes two protrusions located on the two gate stack structures. Hard mask spacers are formed on two sides of each of the two protrusions. A first etching process is performed to remove a portion of the conductive material layer by using the hard mask spacers as a mask. A second etching process is performed to completely remove the hard mask spacers. Then, a third etching process is performed on the conductive material layer to form a first conductive spacer and a second conductive spacer located on one side and the other side of the two gate stack structures and to form a conductive layer located between the two gate stack structures.

公开(公告)号：US20230027508A1

公开(公告)日：2023-01-26

申请号：US17396493

申请日：2021-08-06

Applicant: United Microelectronics Corp.

Inventor： Kai Jiun Chang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H01L45/00

Abstract: Provided are a resistive random access memory (RRAM) and a manufacturing method thereof. The resistive random access memory includes multiple unit structures disposed on a substrate. Each of the unit structures includes a first electrode, a first metal oxide layer, and a spacer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. The spacer is disposed on sidewalls of the first electrode and the first metal oxide layer. In addition, the resistive random access memory includes a second metal oxide layer and a second electrode. The second metal oxide layer is disposed on the unit structures and is connected to the unit structures. The second electrode is disposed on the second metal oxide layer.

公开(公告)号：US20230025163A1

公开(公告)日：2023-01-26

申请号：US17404939

申请日：2021-08-17

Applicant: United Microelectronics Corp.

Inventor： Wen Wen Gong ,  Xiaofei Han ,  Chow Yee Lim ,  Hong Liao ,  Jun Qian

IPC: H01L21/308 ,  H01L27/11556

Abstract: A method of manufacturing a semiconductor structure including the following steps is provided. A substrate is provided. The substrate has a first region and a second region. A stacked structure is formed on the substrate in the first region. The stacked structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, a first conductive layer, and a first hard mask layer. A dielectric material layer is formed on the substrate in the second region. A second conductive layer is formed on the dielectric material layer in the second region. A first patterned photoresist layer is formed. The first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed by using the first patterned photoresist layer as a mask.