公开(公告)号：US10261584B2

公开(公告)日：2019-04-16

申请号：US15234141

申请日：2016-08-11

Applicant: Rambus Inc.

Inventor： Patrick R. Gill ,  David G. Stork ,  Thomas Vogelsang

IPC: G06F3/042 ,  G06F3/01 ,  G06F1/16 ,  H04N5/247 ,  G02B5/18

Abstract: A user interface includes both a touchscreen for tactile input and one or more lensless optical sensors for sensing additional, remote gestures. Users can interact with the user interface in a volume of space near the display, and are thus not constrained to the relatively small area of the touchscreen. Remote hand or face gestures can be used to turn on or otherwise alter the tactile user interface. Shared user interfaces can operate without touch, and thus avoid cross-contamination of e.g. viruses and bacteria.

公开(公告)号：US10250240B2

公开(公告)日：2019-04-02

申请号：US15823226

申请日：2017-11-27

Applicant: Rambus Inc.

Inventor： Brian Hing-Kit Tsang ,  Jared L. Zerbe

IPC: G11C11/16 ,  H03K5/133 ,  G11C8/18 ,  H03L7/00 ,  G11C7/10 ,  G11C7/22 ,  G06F13/16 ,  H03K3/03 ,  H03K7/06 ,  H01L43/08 ,  G11C11/15 ,  H03K5/00

Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.

公开(公告)号：US10225111B2

公开(公告)日：2019-03-05

申请号：US15907205

申请日：2018-02-27

Applicant: Rambus Inc.

Inventor： Vladimir M. Stojanovic ,  Andrew C. Ho ,  Anthony Bessios ,  Bruno W. Garlepp ,  Grace Tsang ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Jason C. Wei

IPC: H04L25/03 ,  H04L25/06 ,  H04L25/497 ,  H04L7/027

Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

公开(公告)号：US10222742B2

公开(公告)日：2019-03-05

申请号：US15458871

申请日：2017-03-14

Applicant: Rambus Inc.

Inventor： Patrick R. Gill ,  David G. Stork ,  Mehjabin Sultana Monjur ,  Luke A. Pfister

IPC: G02B5/18 ,  G03H1/04 ,  H01L27/146 ,  H04N5/225 ,  G03H1/02

Abstract: An optical phase grating produces an interference pattern rich in intensity and spatial-frequency information from the external scene. The grating includes an odd number of repeated sets of adjacent horizontal portions, separated by steps, that fill an area that radiates outward from a central region. At a given distance from the central region and within the area of the phase grating, each of the first horizontal portions is of a first width that differs from a second width of the adjacent second horizontal portions. The interference patterns produced by the grating can be processed to extract images and other information of interest about an imaged scene.

公开(公告)号：US20190065207A1

公开(公告)日：2019-02-28

申请号：US16026733

申请日：2018-07-03

Applicant: Rambus Inc.

Inventor： William C. MOYER ,  Jeffrey W. SCOTT

IPC: G06F9/38 ,  G06F11/10 ,  G06F9/30

CPC classification number: G06F9/3875 ,  G06F9/3004 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1076

Abstract: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

公开(公告)号：US10211972B2

公开(公告)日：2019-02-19

申请号：US15629453

申请日：2017-06-21

Applicant: Rambus Inc.

Inventor： Mehrdad Ramezani ,  David J. Cassan ,  Christopher D. Holdenried ,  Sang-Wook Paul Park ,  Marcus Van Ierssel

IPC: H04L7/00 ,  H04L25/03 ,  H03L7/081 ,  H04L7/033

Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

公开(公告)号：US10210102B2

公开(公告)日：2019-02-19

申请号：US15485115

申请日：2017-04-11

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Frederick A. Ware

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/14 ,  G06F12/02

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

公开(公告)号：US20190052490A1

公开(公告)日：2019-02-14

申请号：US16113900

申请日：2018-08-27

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Maruf H. Mohammad

IPC: H04L25/49 ,  H04L25/03

Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.

公开(公告)号：US10204662B2

公开(公告)日：2019-02-12

申请号：US15603333

申请日：2017-05-23

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/02 ,  G11C5/06 ,  H01L23/48 ,  H01L27/108 ,  H01L25/065

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

公开(公告)号：US10204063B2

公开(公告)日：2019-02-12

申请号：US15867646

申请日：2018-01-10

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F12/00 ,  G06F13/16 ,  G06F12/06 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G06F12/02

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.